DS1307
SCL (Serial Clock Input)
- SCL is used to synchronize data movement on the serial interface.
SDA (Serial Data Input/Output) -
SDA is the input/output pin for the 2-wire serial interface. The SDA
pin is open drain which requires an external pullup resistor.
SQW/OUT (Square Wave/ Output Driver) -
When enabled, the SQWE bit set to 1, the SQW/OUT pin
outputs one of four square wave frequencies (1 Hz, 4 kHz, 8 kHz, 32 kHz). The SQW/OUT pin is open
drain which requires an external pullup resistor. SQW/OUT will operate with either Vcc or Vbat applied.
X1, X2
- Connections for a standard 32.768 kHz quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (CL) of 12.5 pF.
For more information on crystal selection and crystal layout considerations, please consult Application
Note 58, “Crystal Considerations with Dallas Real Time Clocks.” The DS1307 can also be driven by an
external 32.768 kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator
signal and the X2 pin is floated.
Please review Application Note 95, “Interfacing the DS1307 with a 8051-Compatible Microcontroller”
for additional information.
RTC AND RAM ADDRESS MAP
The address map for the RTC and RAM registers of the DS1307 is shown in Figure 2. The real time
clock registers are located in address locations 00h to 07h. The RAM registers are located in address
locations 08h to 3Fh. During a multi-byte access, when the address pointer reaches 3Fh, the end of RAM
space, it wraps around to location 00h, the beginning of the clock space.
DS1307 ADDRESS MAP
Figure 2
00H
SECONDS
MINUTES
HOURS
DAY
DATE
MONTH
YEAR
07H
08H
3FH
CONTROL
RAM
56 x 8
CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. The real time
clock registers are illustrated in Figure 3. The time and calendar are set or initialized by writing the
appropriate register bytes. The contents of the time and calendar registers are in the Binary-Coded
Decimal (BCD) format. Bit 7 of Register 0 is the Clock Halt (CH) bit. When this bit is set to a 1, the
oscillator is disabled. When cleared to a 0, the oscillator is enabled.
Please note that the initial power on state of all registers is not defined. Therefore it is important to
enable the oscillator (CH bit=0) during initial configuration.
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DALLAS [ DALLAS SEMICONDUCTOR ]
