DS1305
TIME OF DAY ALARM MASK BITS Table 1
ALARM REGISTER MASK BITS (BIT 7)
SECONDS MINUTES
HOURS
DAYS
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
1
1
0
Alarm once per second
Alarm when seconds match
Alarm when minutes and seconds match
Alarm hours, minutes and seconds match
Alarm day, hours, minutes and seconds match
SPECIAL PURPOSE REGISTERS
The DS1305 has three additional registers (Control Register, Status Register and Trickle Charger
Register) that control the real time clock, interrupts and trickle charger.
CONTROL REGISTER (READ 0FH, WRITE 8FH)
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
EOSC
WP
0
0
0
INTCN
AIE1
AIE0
EOSC (Enable oscillator) - This bit when set to logic 0 will start the oscillator. When this bit is set to a
logic 1, the oscillator is stopped and the DS1305 is placed into a low-power standby mode with a current
drain of less than 100 nanoamps when power is supplied by VBAT or VCC2 . The initial power on state is
not defined.
WP (Write Protect) - Before any write operation to the clock or RAM, this bit must be logic 0. When
high, the write protect bit prevents a write operation to any register, including bits 0, 1, 2 and 7 of the
control register. Upon initial power up, the state of the WP bit is undefined. Therefore the WP bit should
be cleared before attempting to write to the device.
INTCN (Interrupt Control) - This bit controls the relationship between the two time of day alarms and
the interrupt output pins. When the INTCN bit is set to a logic 1, a match between the timekeeping
registers and the Alarm 0 registers will activate the INT0 pin (provided that the alarm is enabled) and a
match between the timekeeping registers and the Alarm 1 registers will activate the INT1 pin (provided
that the alarm is enabled). When the INTCN bit is set to a logic 0, a match between the timekeeping
registers and either Alarm 0 or Alarm 1 will activate the INT0 pin (provided that the alarms are enabled).
INT1 has no function when INTCN is set to a logic 0.
AIE0 (Alarm Interrupt Enable 0) - When set to a logic 1, this bit permits the Interrupt 0 Request Flag
(IRQF0) bit in the status register to assert INT0 . When the AIE0 bit is set to logic 0, the IRQF0 bit does
not initiate the INT0 signal.
AIE1 (Alarm Interrupt Enable 1) - When set to a logic 1, this bit permits the Interrupt 1 Request Flag
(IRQF1) bit in the status register to assert INT1 (when INTCN=1) or to assert INT0 (when INTCN=0).
When the AIE1 bit is set to logic 0, the IRQF1 bit does not initiate an interrupt signal.
7 of 22
DALLAS [ DALLAS SEMICONDUCTOR ]
