DS1305
SPI SINGLE-BYTE READ Figure 8
*SCLK can be either polarity.
The address byte is always the first byte entered after CE is driven high. The most significant bit (A7) of
this byte determines if a read or write will take place. If A7 is 0, one or more read cycles will occur. If
A7 is 1, one or more write cycles will occur.
Data transfers can occur 1 byte at a time or in multiple-byte burst mode. After CE is driven high an
address is written to the DS1305. After the address, one or more data bytes can be written or read. For a
single-byte transfer 1 byte is read or written and then CE is driven low. For a multiple-byte transfer,
however, multiple bytes can be read or written to the DS1305 after the address has been written. Each
read or write cycle causes the RTC register or RAM address to automatically increment. Incrementing
continues until the device is disabled. When the RTC is selected, the address wraps to 00h after
incrementing to 1Fh (during a read) and wraps to 80h after incrementing to 9Fh (during a write). When
the RAM is selected, the address wraps to 20h after incrementing to 7Fh (during a read) and wraps to A0h
after incrementing to FFh (during a write).
SPI MULTIPLE-BYTE BURST TRANSFER Figure 9
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DALLAS [ DALLAS SEMICONDUCTOR ]
