DS1075
Figure 7
Depending on the relative timing of the
SELX
signal and the internal clock, there may be up to one full
cycle of t
I
on the output after the falling edge of
SELX
. Then, the “low” time (t
LOW
) between output
pulses will be dependent on the relative timing between t
I
and t
E
. The time interval between the falling
edge of
SELX
and the first rising edge of the externally derived clock is t
SIE
. Approximate maximum and
minimum values of these parameters are:
t
LOW
(min) = t
I
/2
t
LOW
(max) = t
I
/2 + t
E
t
SIE
(min) = t
I
/2
t
SIE
(max) = 3 t
I
/2 + t
E
NOTE:
In each case there will be a small additional delay due to internal propagation delays.
FROM EXTERNAL TO INTERNAL CLOCK
This is accomplished by a low to high transition on the
SELX
pin. In this case the switch is level
triggered, to allow for the possibility of a clock signal not being present at OSCIN. Note therefore, that if
a constant high-level signal is applied to OSCIN it will not be possible to switch over to the internal
reference. (Level triggering was not employed for the switch from internal to external reference as this
approach is slower and the internal clock may be running at a much higher frequency than the maximum
allowed external clock rate). When
SELX
is high and a low level is sensed on EXTCLK, OUT0 will be
held low until a falling edge occurs on INTCLK, then the next rising edge of INTCLK will be routed
through to OUT0.
Figure 8
Depending on the relative timing of the
SELX
signal and the external clock, there may be up to one full t
E
high period on the output after the rising edge of
SELX
. Then, the “low” time (t
LOW
) between output
pulses will be dependent on the relative timing between t
I
and t
E
. The time interval between the falling
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DALLAS [ DALLAS SEMICONDUCTOR ]
