DS1075
Table 2
E/I
MSEL
DIV1
M
BIT
0
BIT
0
BIT*
BIT
OPERATION
0
0
0
1
0
1
0
INTERNAL OSCILLATOR DIVIDED BY 4*N
INTERNAL OSCILLATOR DIVIDED BY 2*N
INTERNAL OSCILLATOR DIVIDED BY N
EXTERNAL OSCILLATOR DIVIDED BY N
INTERNAL OSCILLATOR DIVIDED BY 1
EXTERNAL OSCILLATOR DIVIDED BY 1
0
0
1
0
1
X
0
X
X
X
X
1
X
1
X
*Assuming PDN bit = 1, otherwise internal/external selection will be controlled by the PDN /SELX pin.
DIV WORD Figure 3
(MSB)
(LSB)
N (9-BITS)
PDN
This bit is used to determine the function of the PDN /SELX pin. If PDN=0, the PDN /SELX pin can be
used to determine the timing reference (either the internal oscillator or an external reference/crystal). If
PDN=1, the PDN /SELX pin is used to put the device into power-down mode.
EN0
This bit is used to determine whether the OUT0 pin is active or not. If EN0 =1, OUT0 is disabled (High-
impedance). If EN0 =0, the internal reference clock (MCLK) is output from OUT0. The OE pin has no
effect on OUT0, but OUT0 is disabled as part of the power-down sequence.
N
These nine bits determine the value of the programmable divider. The range of divisor values is from 2 to
513, and is equal to the programmed value of N plus 2:
Table 3
BIT
DIVISOR (N)
VALUES
000000000
VALUE
2
000000001
3
.
.
.
.
.
.
.
.
.
.
111111111
513
NOTE:
The maximum value of N is constrained by the minimum output frequency. If the internal clock is
selected, INTOSC/(M*N) must be greater than fOUTmin; if the external clock is selected, EXTCLK/N must
be greater than fOUTmin . (If DIV1=1, then INTOSC or EXTCLK, as applicable, must exceed fOUTmin).
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DALLAS [ DALLAS SEMICONDUCTOR ]
