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12C887 参数 Datasheet PDF下载

12C887图片预览
型号: 12C887
PDF下载: 下载PDF文件 查看货源
内容描述: 实时时钟 [Real Time Clock]
分类和应用: 时钟
文件页数/大小: 19 页 / 195 K
品牌: DALLAS [ DALLAS SEMICONDUCTOR ]
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DS12C887  
REGISTER C  
MSB  
LSB  
BIT 7  
IRQF  
BIT 6  
PF  
BIT 5  
AF  
BIT 4  
UF  
BIT 3  
0
BIT 2  
0
BIT 1  
0
BIT 0  
0
IRQF - The Interrupt Request Flag (IRQF) bit is set to a 1 when one or more of the following are true:  
PF = PIE = 1  
AF = AIE = 1  
UF = UIE = 1  
i.e., IRQF = (PF PIE) + (AF AIE) + (UF UIE)  
Any time the IRQF bit is a 1, the IRQ pin is driven low. Flag bits PF, AF, and UF are cleared after  
Register C is read by the program or when the RESET pin is low.  
PF - The Periodic Interrupt Flag (PF) is a read-only bit which is set to a 1 when an edge is detected on the  
selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a 1  
independent of the state of the PIE bit. When both PF and PIE are 1’s, the IRQ signal is active and will  
set the IRQF bit. The PF bit is cleared by a software read of Register C or a RESET .  
AF - A 1 in the Alarm Interrupt Flag (AF) bit indicates that the current time has matched the alarm time.  
If the AIE bit is also a 1, the IRQ pin will go low and a 1 will appear in the IRQF bit. A RESET or a read  
of Register C will clear AF.  
UF - The Update Ended Interrupt Flag (UF) bit is set after each update cycle. When the UIE bit is set to  
1, the 1 in UF causes the IRQF bit to be a 1, which will assert the IRQ pin. UF is cleared by reading  
Register C or a RESET .  
BIT 3 THROUGH BIT 0 - These are unused bits of the status Register C. These bits always read 0 and  
cannot be written.  
REGISTER D  
MSB  
LSB  
BIT 0  
BIT 7  
VRT  
BIT 6  
0
BIT 5  
0
BIT 4  
0
BIT 3  
0
BIT 2  
0
BIT 1  
0
0
VRT - The Valid RAM and Time (VRT) bit indicates the condition of the battery connected to the VBAT  
pin. This bit is not writeable and should always be a 1 when read. If a 0 is ever present, an exhausted  
internal lithium energy source is indicated and both the contents of the RTC data and RAM data are  
questionable. This bit is unaffected by RESET .  
BIT 6 THROUGH BIT 0 - The remaining bits of Register D are not usable. They cannot be written and,  
when read, they will always read 0.  
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