ES51932
22,000 Counts Auto DMM
Block diagram:
RS232 DATA
SDO
. . .
SCLK
SDATA
uPLCD
μP
ES51932
PLSD DATA
FC1-FC5/SLACDC
Operation timing diagram for PLSD feature is shown as below:
46 clock pulses
tdelay
RS232 data is received
Start to send PLSD data
…
SCLK
SDO
CR
LF
PLSD data
SDATA
tHIG tLOW
tR
tF
SCLK
tHOLD
tSETU
SDATA
Parameter
Symbol Min. Typ. Max. Unit
SCLK clock frequency
SCLK clock time “L”
SCLK clock time “H”
Data input setup time
Data input hold time
fSCLK
tLOW
tHIGH
10
4.7
4.0
-
-
-
100 KHz
-
us
-
tSETUP 200
ns
tHOLD 100
SCLK/SDATA rising time
tR
tF
1.0
us
SCLK/SDATA falling time
SCLK delay time after
receiving RS232
0.3
tdelay
0.1
100
ms
Ver. 1.2
29
10/05/27
CYRUSTEK [ Cyrustek corporation ]
