W256
Pin Summary
Name
SEL_DDR
28
Pins
Description
Input to configure for DDR-ONLY mode or STANDARD SDRAM mode.
1 = DDR-ONLY mode.
0 = STANDARD SDRAM mode.
When SEL_DDR is pulled HIGH or configured for DDR-ONLY mode, all the buffers
will be configured as DDR outputs.
Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode.
When SEL_DDR is pulled LOW or configured for STANDARD SDRAM output, all
the buffers will be configured as STANDARD SDRAM outputs.
Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM mode.
SMBus clock input.
SMBus data input.
Reference input from chipset.
2.5V input for DDR-ONLY mode; 3.3V input for
STANDARD SDRAM mode.
Feedback clock for chipset.
Output voltage depends on VDD3.3_2.5V.
Active LOW input to enable Power Down mode; all outputs will be pulled LOW.
Clock outputs.
These outputs provide copies of BUF_IN. Voltage swing depends
on VDD3.3_2.5 power supply.
Clock outputs.
These outputs provide complementary copies of BUF_IN when
SEL_DDR is active. These outputs provide copies of BUF_IN when SEL_DDR is
inactive. Voltage swing depends on VDD3.3_2.5 power supply.
Connect to 2.5V power supply when W256 is configured for DDR-ONLY mode.
Connect to 3.3V power supply, when W256 is configured for standard SDRAM
mode.
Ground.
SCLK
SDATA
BUF_IN
FBOUT
PWR_DWN#
DDR[0:5]T_SDRAM
[0,2,4,6,8,10]
16
15
10
1
2
3, 7, 12, 19, 23, 27
DDR[0:5]C_SDRAM 4, 8, 13, 18, 22, 26
[1,3,5,7,9, 11]
VDD3.3_2.5
5, 9, 14, 21, 25
GND
6, 11, 17, 20, 24
Document #: 38-07256 Rev. *C
Page 2 of 9
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