CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
2. Register Reference
Register Map Bank 1 Table: Configuration Space
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
USBIO_CR2
USB_CR1
C0
C1
RW
#
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PMA0_WA
PMA1_WA
PMA2_WA
PMA3_WA
PMA4_WA
PMA5_WA
PMA6_WA
PMA7_WA
RW
RW
RW
RW
RW
RW
RW
RW
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
RW
RW
RW
RW
RW
RW
RW
RW
EP1_CR0
EP2_CR0
EP3_CR0
EP4_CR0
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
#
#
#
#
PMA0_RA
PMA1_RA
PMA2_RA
PMA3_RA
PMA4_RA
PMA5_RA
PMA6_RA
PMA7_RA
RW
RW
RW
RW
RW
RW
RW
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
RW
RW
RW
RW
PRT7DM0
PRT7DM1
PRT7IC0
PRT7IC1
DBB00FN
DBB00IN
DBB00OU
RW
RW
RW
RW
RW
RW
RW
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
RW
RW
RW
RW
RW
RW
RW
R
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
CMP_GO_EN
CMP_GO_EN1
AMD_CR1
ALT_CR0
RW
RW
RW
RW
RW
RW
RW
RW
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
VLT_CMP
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
MUX_CR4
MUX_CR5
W
W
RW
W
RW
RW
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RW
RW
RW
RW
RW
RW
RW
CPU_F
RL
DAC_CR
CPU_SCR1
CPU_SCR0
RW
#
#
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
February 15, 2007
Document No. 38-12018 Rev. *J
21
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