CY7C9689-AC 参数 Datasheet PDF下载

CY7C9689

Pin Descriptions

(continued)

Pin

18

Name

TXEN

I/O Characteristics

Signal Description

TTL input, sampled on Transmit Enable.

TXCLK¦ or REFCLK¦ TXEN is sampled on the rising edge of the TXCLK or REFCLK input and enables

Internal Pull-Up

parallel data bus write operations (when selected). The device is selected when

TXEN is asserted during a clock cycle immediately following one in which CE

is sampled LOW.

Depending on the level on EXTFIFO, the asserted state for TXEN can be active

HIGH or active LOW. If EXTFIFO is LOW, then TXEN is active LOW and data

is captured on the same clock cycle where TXEN is sampled LOW. If EXTFIFO

is HIGH, then TXEN is active HIGH and data is captured on the clock cycle

following any clock edge when TXEN is sampled HIGH.

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TXBISTEN

TTL input,

asynchronous

Internal Pull-Up

Transmitter BIST Enable.

When TXBISTEN is LOW, the transmitter generates a 511-character repeating

sequence that can be used to validate link integrity. This 4B/5B BIST sequence

is generated regardless of the state of other configuration inputs. The transmit-

ter returns to normal operation when TXBISTEN is HIGH. All Transmit FIFO

read operations are suspended when BIST is active.

16

TXRST

TTL input, sampled on Reset Transmit FIFO.

TXCLK¦

When the Transmit FIFO is enabled (FIFOBYP is HIGH), TXEN is deasserted,

Internal Pull-Up

CE is asserted (LOW), and TXRST is sampled LOW by TXCLK for seven cycles,

the Transmit FIFO begins its internal reset process. The Transmit FIFO TXFULL

flag is asserted and the host interface counter and address pointer are zeroed.

This reset propagates to the serial transmit side, any remaining counters and

pointers. The TXFULL flag is asserted until both sides of the Transmit FIFO have

reset. While TXRST remains asserted, the Transmit FIFO remains in reset and

the TXFULL output remains asserted.

When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXRST is ignored.

TTL input, sampled on Transmitter Halt Control Input.

TXCLK¦

When TXHALT is asserted LOW, transmission of data is suspended and the

Internal Pull-Up

HOTLink TAXI transmits SYNC characters. When TXHALT is deasserted HIGH,

normal data processing proceeds.

If the Transmit FIFO is enabled (FIFOBYP is HIGH), the interface is allowed to

continue loading data into the Transmit FIFO while TXHALT is asserted.

9

TXHALT

72

TXFULL

Three-state TTL out- Transmit FIFO Full Status Flag.

put, changes following When the Transmit FIFO is enabled (FIFOBYP is HIGH) and its flags are driven

TXCLK¦ or REFCLK¦ (CE is LOW), TXFULL is asserted when four or fewer characters can be written

to the HOTLink Transmit FIFO. If a Transmit FIFO reset has been initiated

(TXRST was sampled asserted for a minimum of seven TXCLK cycles),

TXFULL is asserted to enforce the full/unavailable status of the Transmit FIFO

during reset.

When the Transmit FIFO is bypassed (FIFOBYP is LOW), the TXFULL output

changes after the rising edge of REFCLK. TXFULL is asserted when the trans-

mitter is BUSY (not accepting a new data or command characters) and deas-

serted when new characters can be accepted.

When the Transmit FIFO is bypassed and RANGESEL is HIGH or SPDSEL is

LOW, TXFULL toggles at the character rate to provide a character rate reference

control-indication since REFCLK is operating at twice of the data rate.

The asserted state of this output (HIGH or LOW) is determined by the state of

the EXTFIFO input. When EXTFIFO is LOW, TXFULL is active LOW. When

EXTFIFO is HIGH, TXFULL is active HIGH.

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