CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 12. FX2LP Register Summary (continued)
Hex Size Name
Description
b7
0
b6
b5
b4
b3
b2
b1
b0
Default
Access
[12]
E65D 1
E65E 1
USBIRQ
USB Interrupt Requests
EP0ACK
EP6
HSGRANT URES
SUSP
EP1OUT
SUTOK
EP1IN
SOF
SUDAV
EP0IN
0xxxxxxx rbbbbbbb
00000000 RW
EPIE
Endpoint Interrupt
Enables
EP8
EP4
EP4
EP2
EP2
EP0OUT
[12]
E65F 1
EPIRQ
Endpoint Interrupt
Requests
EP8
EP6
EP1OUT
EP1IN
EP0OUT
EP0IN
0
RW
[11]
[11]
E660
E661
E662
1
1
1
GPIFIE
GPIF Interrupt Enable
GPIF Interrupt Request
0
0
0
0
0
0
0
0
0
0
GPIFWF
GPIFWF
0
GPIFDONE 00000000 RW
GPIFDONE 000000xx RW
GPIFIRQ
0
0
0
0
USBERRIE
USB Error Interrupt
Enables
ISOEP8
ISOEP6
ISOEP4
ISOEP2
ERRLIMIT
ERRLIMIT
LIMIT0
00000000 RW
[12]
E663
E664
1
1
USBERRIRQ
USB Error Interrupt
Requests
ISOEP8
EC3
ISOEP6
EC2
ISOEP4
EC1
ISOEP2
EC0
0
0
0
0000000x bbbbrrrb
xxxx0100 rrrrbbbb
ERRCNTLIM
USB Error counter and
limit
LIMIT3
LIMIT2
LIMIT1
E665
E666
1
1
CLRERRCNT
INT2IVEC
Clear Error Counter EC3:0 x
x
x
x
x
x
x
x
xxxxxxxx W
Interrupt 2 (USB)
Autovector
0
1
0
I2V4
I2V3
I2V2
I2V1
I2V0
0
0
00000000 R
10000000 R
00000000 RW
E667
1
INT4IVEC
Interrupt 4 (slave FIFO &
GPIF) Autovector
0
0
I4V3
0
I4V2
0
I4V1
I4V0
0
0
0
E668
E669
1
7
INTSET-UP
reserved
Interrupt 2&4 setup
AV2EN
INT4SRC
AV4EN
INPUT / OUTPUT
PORTACFG
E670
E671
E672
1
1
1
I/O PORTA Alternate
Configuration
FLAGD
GPIFA7
GPIFA8
SLCS
GPIFA6
T2EX
0
0
0
0
INT1
INT0
00000000 RW
00000000 RW
00000000 RW
PORTCCFG
PORTECFG
I/O PORTC Alternate
Configuration
GPIFA5
INT6
GPIFA4
GPIFA3
GPIFA2
GPIFA1
T1OUT
GPIFA0
T0OUT
I/O PORTE Alternate
Configuration
RXD1OUT RXD0OUT T2OUT
E673
E677
E678
4
1
1
reserved
reserved
2
I CS
I²C Bus
START
STOP
d6
LASTRD
ID1
d4
0
ID0
d3
0
BERR
d2
ACK
d1
DONE
d0
000xx000 bbbrrrrr
xxxxxxxx RW
00000000 RW
xxxxxxxx RW
xxxxxxxx RW
Control & Status
E679
1
I2DAT
I²C Bus
Data
d7
0
d5
0
2
E67A 1
E67B 1
E67C 1
I CTL
I²C Bus
Control
0
0
STOPIE
D1
400KHZ
D0
XAUTODAT1
XAUTODAT2
UDMA CRC
Autoptr1 MOVX access, D7
when APTREN=1
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
Autoptr2 MOVX access, D7
when APTREN=1
D1
D0
[11]
E67D 1
E67E 1
E67F 1
UDMACRCH
UDMA CRC MSB
UDMA CRC LSB
UDMA CRC Qualifier
CRC15
CRC14
CRC6
0
CRC13
CRC5
0
CRC12
CRC4
0
CRC11
CRC3
CRC10
CRC2
CRC9
CRC1
CRC8
CRC0
01001010 RW
10111010 RW
[11]
UDMACRCL
CRC7
UDMACRC-
QUALIFIER
QENABLE
QSTATE
QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb
USB CONTROL
USBCS
E680
E681
E682
E683
E684
E685
E686
E687
E688
1
1
1
1
1
1
1
1
2
USB Control & Status
Put chip into suspend
HSM
x
0
0
0
DISCON
NOSYNSOF RENUM
SIGRSUME x0000000 rrrrbbbb
SUSPEND
WAKEUPCS
TOGCTL
x
x
x
x
x
x
x
xxxxxxxx W
Wakeup Control & Status WU2
WU
S
WU2POL
WUPOL
I/O
0
DPEN
EP2
FC10
FC2
MF2
FA2
WU2EN
EP1
FC9
FC1
MF1
FA1
WUEN
EP0
FC8
FC0
MF0
FA0
xx000101 bbbbrbbb
x0000000 rrrbbbbb
00000xxx R
Toggle Control
Q
R
EP3
0
USBFRAMEH
USBFRAMEL
MICROFRAME
FNADDR
USB Frame count H
USB Frame count L
Microframe count, 0-7
USB Function address
0
0
0
0
FC7
0
FC6
0
FC5
0
FC4
0
FC3
0
xxxxxxxx
00000xxx R
0xxxxxxx
R
0
FA6
FA5
FA4
FA3
R
reserved
ENDPOINTS
[11]
E68A 1
E68B 1
E68C 1
E68D 1
EP0BCH
Endpoint 0 Byte Count H (BC15)
Endpoint 0 Byte Count L (BC7)
(BC14)
BC6
(BC13)
BC5
(BC12)
BC4
(BC11)
BC3
(BC10)
BC2
(BC9)
BC1
(BC8)
BC0
xxxxxxxx RW
xxxxxxxx RW
[11]
EP0BCL
reserved
EP1OUTBC
Endpoint 1 OUT Byte
Count
0
BC6
BC5
BC4
BC3
BC2
BC1
BC0
0xxxxxxx RW
E68E 1
E68F 1
reserved
EP1INBC
Endpoint 1 IN Byte Count 0
Endpoint 2 Byte Count H
Endpoint 2 Byte Count L BC7/SKIP
BC6
0
BC5
0
BC4
0
BC3
0
BC2
BC10
BC2
BC1
BC9
BC1
BC0
BC8
BC0
0xxxxxxx RW
00000xxx RW
xxxxxxxx RW
[11]
E690
E691
E692
E694
E695
E696
E698
E699
1
1
2
1
1
2
1
1
EP2BCH
0
[11]
EP2BCL
BC6
BC5
BC4
BC3
reserved
[11]
EP4BCH
Endpoint 4 Byte Count H
0
0
0
0
0
0
BC9
BC1
BC8
BC0
000000xx RW
xxxxxxxx RW
[11]
EP4BCL
Endpoint 4 Byte Count L BC7/SKIP
BC6
BC5
BC4
BC3
BC2
reserved
[11]
EP6BCH
Endpoint 6 Byte Count H
0
0
0
0
0
BC10
BC2
BC9
BC1
BC8
BC0
00000xxx RW
xxxxxxxx RW
[11]
EP6BCL
Endpoint 6 Byte Count L BC7/SKIP
BC6
BC5
BC4
BC3
E69A 2
E69C 1
reserved
[11]
EP8BCH
Endpoint 8 Byte Count H
0
0
0
0
0
0
BC9
BC8
000000xx RW
Document #: 38-08032 Rev. *N
Page 31 of 62
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