CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
5. Register Summary
FX2LP register bit definitions are described in the FX2LP TRM in greater detail.
Table 12. FX2LP Register Summary
Hex Size Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default
Access
GPIF Waveform Memories
E400 128 WAVEDATA
GPIF Waveform
Descriptor 0, 1, 2, 3 data
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
E480 128 reserved
GENERAL CONFIGURATION
E50D
GPCR2
General Purpose Configu-reserved
ration Register 2
reserved
0
reserved
FULL_SPEE reserved
D_ONLY
reserved
reserved
reserved
00000000 R
E600
E601
1
1
CPUCS
CPU Control & Status
0
PORTCSTB CLKSPD1 CLKSPD0 CLKINV
CLKOE
IFCFG1
8051RES
IFCFG0
00000010 rrbbbbbr
10000000 RW
IFCONFIG
Interface Configuration
(Ports, GPIF, slave FIFOs)
IFCLKSRC 3048MHZ
IFCLKOE
FLAGB1
FLAGD1
0
IFCLKPOL ASYNC
GSTATE
FLAGA2
FLAGC2
EP2
[11]
[11]
E602
E603
E604
1
1
1
PINFLAGSAB
Slave FIFO FLAGA and FLAGB3
FLAGB Pin Configuration
FLAGB2
FLAGD2
0
FLAGB0
FLAGD0
0
FLAGA3
FLAGC3
EP3
FLAGA1
FLAGC1
EP1
FLAGA0
FLAGC0
EP0
00000000 RW
00000000 RW
PINFLAGSCD
Slave FIFO FLAGC and FLAGD3
FLAGD Pin Configuration
[11]
FIFORESET
Restore FIFOS to default NAKALL
state
xxxxxxxx W
E605
E606
E607
E608
1
1
1
1
BREAKPT
BPADDRH
BPADDRL
UART230
Breakpoint Control
0
0
0
0
BREAK
A11
A3
BPPULSE BPEN
0
00000000 rrrrbbbr
xxxxxxxx RW
xxxxxxxx RW
Breakpoint Address H
Breakpoint Address L
A15
A7
0
A14
A6
0
A13
A5
0
A12
A4
0
A10
A2
0
A9
A1
A8
A0
230 Kbaud internally
generated ref. clock
0
230UART1 230UART0 00000000 rrrrrrbb
[11]
E609
1
FIFOPINPOLAR
Slave FIFO Interface pins 0
polarity
0
PKTEND
SLOE
rv4
SLRD
rv3
SLWR
rv2
EF
FF
00000000 rrbbbbbb
E60A 1
E60B 1
REVID
Chip Revision
rv7
rv6
0
rv5
0
rv1
rv0
RevA
00000001
R
[11]
REVCTL
Chip Revision Control
0
0
0
0
0
dyn_out
enh_pkt
00000000 rrrrrrbb
UDMA
E60C 1
3
GPIFHOLDAMOUNT MSTB Hold Time
(for UDMA)
0
0
0
0
0
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
reserved
ENDPOINT CONFIGURATION
E610
E611
1
1
EP1OUTCFG
Endpoint 1-OUT
Configuration
VALID
VALID
0
0
TYPE1
TYPE1
TYPE0
TYPE0
0
0
0
0
0
0
0
0
10100000 brbbrrrr
10100000 brbbrrrr
EP1INCFG
Endpoint 1-IN
Configuration
E612
E613
E614
E615
1
1
1
1
2
1
EP2CFG
EP4CFG
EP6CFG
EP8CFG
reserved
Endpoint 2 Configuration VALID
Endpoint 4 Configuration VALID
Endpoint 6 Configuration VALID
Endpoint 8 Configuration VALID
DIR
DIR
DIR
DIR
TYPE1
TYPE1
TYPE1
TYPE1
TYPE0
TYPE0
TYPE0
TYPE0
SIZE
0
0
0
0
0
BUF1
0
BUF0
0
10100010 bbbbbrbb
10100000 bbbbrrrr
11100010 bbbbbrbb
11100000 bbbbrrrr
SIZE
0
BUF1
0
BUF0
0
[11]
[11]
[11]
[11]
E618
E619
EP2FIFOCFG
Endpoint 2 / slave FIFO
configuration
0
0
0
0
INFM1
INFM1
INFM1
INFM1
OEP1
OEP1
OEP1
OEP1
AUTOOUT AUTOIN
AUTOOUT AUTOIN
AUTOOUT AUTOIN
AUTOOUT AUTOIN
ZEROLENIN 0
ZEROLENIN 0
ZEROLENIN 0
ZEROLENIN 0
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
1
EP4FIFOCFG
EP6FIFOCFG
EP8FIFOCFG
reserved
Endpoint 4 / slave FIFO
configuration
E61A 1
E61B 1
E61C 4
Endpoint 6 / slave FIFO
configuration
Endpoint 8 / slave FIFO
configuration
[11
E620
E621
E622
E623
E624
E625
E626
E627
1
1
1
1
1
1
1
1
EP2AUTOINLENH Endpoint 2 AUTOIN
0
0
0
0
0
PL10
PL2
0
PL9
PL8
PL0
PL8
PL0
PL8
PL0
PL8
PL0
00000010 rrrrrbbb
00000000 RW
Packet Length H
[11]
EP2AUTOINLENL
Endpoint 2 AUTOIN
Packet Length L
PL7
0
PL6
0
PL5
0
PL4
0
PL3
0
PL1
PL9
PL1
PL9
PL1
PL9
PL1
[11]
EP4AUTOINLENH Endpoint 4 AUTOIN
00000010 rrrrrrbb
00000000 RW
Packet Length H
[11]
EP4AUTOINLENL
Endpoint 4 AUTOIN
Packet Length L
PL7
0
PL6
0
PL5
0
PL4
0
PL3
0
PL2
PL10
PL2
0
[11]
EP6AUTOINLENH Endpoint 6 AUTOIN
00000010 rrrrrbbb
00000000 RW
Packet Length H
[11]
EP6AUTOINLENL
Endpoint 6 AUTOIN
Packet Length L
PL7
0
PL6
0
PL5
0
PL4
0
PL3
0
[11]
EP8AUTOINLENH Endpoint 8 AUTOIN
00000010 rrrrrrbb
00000000 RW
Packet Length H
[11]
EP8AUTOINLENL
Endpoint 8 AUTOIN
Packet Length L
PL7
PL6
PL5
PL4
PL3
PL2
E628
E629
1
1
ECCCFG
ECCRESET
ECC1B0
ECC Configuration
ECC Reset
0
0
0
0
0
0
0
ECCM
x
00000000 rrrrrrrb
00000000 W
x
x
x
x
x
x
x
E62A 1
ECC1 Byte 0 Address
LINE15
LINE14
LINE13
LINE12
LINE11
LINE10
LINE9
LINE8
00000000 R
Note
11. Read and writes to these registers may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”
Document #: 38-08032 Rev. *N
Page 29 of 62
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