CY7C65640A
Table 0-1. CY7C65640APin Assignments
Pin
3
7
11
15
19
23
27
33
39
45
55
4
8
12
16
20
24
28
34
40
47
50
56
21
22
46
Name
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XIN
XOUT
RESET#
Type
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Input
Output
Input
Default
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
V
CC
. This signal provides power to the chip.
V
CC
. This signal provides power to the chip.
V
CC
. This signal provides power to the chip.
V
CC
. This signal provides power to the chip.
V
CC
. This signal provides power to the chip.
V
CC
. This signal provides power to the chip.
V
CC
. This signal provides power to the chip.
V
CC
. This signal provides power to the chip.
V
CC
. This signal provides power to the chip.
V
CC
. This signal provides power to the chip.
V
CC
. This signal provides power to the chip.
GND.
Connect to Ground with as short a path as possible.
GND.
Connect to Ground with as short a path as possible.
GND.
Connect to Ground with as short a path as possible.
GND.
Connect to Ground with as short a path as possible.
GND.
Connect to Ground with as short a path as possible.
GND.
Connect to Ground with as short a path as possible.
GND.
Connect to Ground with as short a path as possible.
GND.
Connect to Ground with as short a path as possible.
GND.
Connect to Ground with as short a path as possible.
GND.
Connect to Ground with as short a path as possible.
GND.
Connect to Ground with as short a path as possible.
GND.
Connect to Ground with as short a path as possible.
24-MHz Crystal IN or External Clock Input.
24-MHz Crystal OUT.
Active LOW Reset.
This pin resets the entire chip. It is normally tied to V
CC
through a 100K resistor, and to GND through a 0.1-µF capacitor. Other than this,
no other special power-up procedure is required.
VBUS.
Connect to the VBUS pin of the upstream connector. This signal indicates
to the hub that it is in a powered state, and may enable the D+ pull-up resistor
to indicate a connection. (The hub will do so after the external EEPROM is read,
unless it is put into a high speedhigh speedhigh speed mode by the upstream
hub). The hub can not be bus powered, and the VBUS signal must not be used
as a power source.
SPI Chip Select.
Connect to CS pin of the EEPROM.
SPI Clock.
Connect to EEPROM SCK pin.
SPI Dataline Connect to GND
with 15-KΩ resistor and to the Data I/O pins of
the EEPROM.
Upstream D– Signal.
Upstream D+ Signal.
26
BUSPOWER
Input
N/A
SPI INTERFACE
25
48
49
SPI_CS
SPI_SCK
SPI_SD
O
O
I/O/Z
O
O
Z
UPSTREAM PORT
17
18
D–
D+
I/O/Z
I/O/Z
Z
Z
Document #: 38-08019 Rev. *J
Page 6 of 23
CYPRESS [ CYPRESS SEMICONDUCTOR ]
