FOR
FOR
enCoRe™
USB
CY7C63221/31A
3.0
Logic Block Diagram
XTALIN/P2.1
XTALOUT
XTALIN/P2.1
XTALOUT/P2.2
Internal
Oscillator
Xtal
Oscillator
W ake-Up
Timer
RAM
96 Bytes
12-bit
Timer
EPROM
3 Kbytes
Brown-Out
Reset
W atch Dog
Timer
Low Voltage
Reset
8-bit
RISC
Core
Interrupt
Controller
USB
Engine
Port 0
GPIO
Port 1
GPIO
3.3V
Regulator
USB &
PS/2
Xcvr
VREG/P2.0
D+ D-
P0.0-P0.7 P1.0-P1.1
4.0
Pin Configurations
(Top View)
CY7C63221A
16-pin PDIP
P0.0
P0.1
P0.2
P0.3
V
SS
V
PP
VREG/P2.0
XTALIN/P2.1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P0.4
P0.5
P0.6
P0.7
D+/SCLK
D–/SDATA
V
CC
XTALOUT/P2.2
5.0
Pin Assignments
CY7C63231A/
CY7C63221A-XC
Name
I/O
I/O
I/O
16-Pin
11
12
1, 2, 3, 4,
13, 14, 15, 16
18-Pin/Pad
12
13
1, 2, 3, 4,
15, 16, 17, 18
Description
USB differential data lines (D– and D+), or PS/2 clock and data
signals (SDATA and SCLK)
GPIO Port 0 capable of sinking up to 50 mA/pin, or sinking
controlled low or high programmable current. Can also source
2 mA current, provide a resistive pull-up, or serve as a high-
impedance input.
IO Port 1 capable of sinking up to 50 mA/pin, or sinking controlled
low or high programmable current. Can also source 2 mA current,
provide a resistive pull-up, or serve as a high-impedance input.
Page 7 of 50
D–/SDATA,
D+/SCLK
P0[7:0]
P1[1:0]
I/O
NA
5,14
Document #: 38-08028 Rev. *B
Vpp
VREG/P2.0
XTALIN/P2.1
XTALOUT/P2.2
Vcc
D-/SDATA
7
8
9
10
11
12
P0.0
P0.1
P0.2
P0.3
P1.0
V
SS
V
PP
VREG/P2.0
XTALIN/P2.1
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P0.4
P0.5
P0.6
P0.7
P1.1
D+/SCLK
D–/SDATA
V
CC
XTALOUT/P2.2
P0.3
P1.0
4
5
18 P0.4
17 P0.5
16 P0.6
15 P0.7
14 P1.1
13 D+/SCLK
Vss
6
3 P0.2
2 P0.1
1 P0.0
CY7C63231A
18-pin SOIC/PDIP
CY7C63221A-XC/XWC
DIE
CYPRESS [ CYPRESS SEMICONDUCTOR ]
