CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
10.4
Data Memory Write
t
CL
CLKOUT
A[15..0]
t
AV
t
t
t
STBL
STBH
AV
WR#
CS#
t
SCSL
t
ON1
t
OFF1
data out
D[7..0]
Stretch = 1
t
CL
CLKOUT
A[15..0]
t
AV
WR#
CS#
t
ON1
t
OFF1
data out
D[7..0]
Figure 10-3. Data Memory Write Timing Diagram
Table 10-3. Data Memory Write Parameters
Parameter Description
Min.
Max.
10.7
11.2
11.2
13.0
13.1
13.1
Unit
ns
Notes
tAV
Delay from Clock to Valid Address
Clock to WR Pulse LOW
Clock to WR Pulse HIGH
Clock to CS Pulse LOW
Clock to Data Turn-on
0
0
0
tSTBL
tSTBH
tSCSL
tON1
ns
ns
ns
0
0
ns
tOFF1
Clock to Data Hold Time
ns
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 will only be active while
either RD# or WR# are active. The address of AUTOPTR2 will be active throughout the cycle and meet the above address valid
time for which is based on the stretch value.
Document #: 38-08032 Rev. *K
Page 40 of 60
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