CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 4-1. FX2LP Pin Descriptions (continued)[10]
128 100 56 56 56
TQFP TQFP SSOP QFN VFBGA
Name
Type Default
Description
70
55
37
30
7G
CTL1 or
FLAGB
O/Z
H
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status
flag signal.
Defaults to FULL for the FIFO selected by the
FIFOADR[1:0] pins.
71
56
38
31
8H
CTL2 or
FLAGC
O/Z
H
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status
flag signal.
Defaults to EMPTY for the FIFO selected by the
FIFOADR[1:0] pins.
66
67
98
32
51
52
76
26
CTL3
CTL4
CTL5
O/Z
H
H
H
Z
CTL3 is a GPIF control output.
CTL4 is a GPIF control output.
CTL5 is a GPIF control output.
Output
Output
I/O/Z
20
13
2G
IFCLK on
CY7C68013A
Interface Clock, used for synchronously clocking data
into or out of the slave FIFOs. IFCLK also serves as a
timing reference for all slave FIFO control signals and
GPIF. When internal clocking is used (IFCONFIG.7 = 1)
the IFCLK pin can be configured to output 30/48 MHz
by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be
inverted, whether internally or externally sourced, by
setting the bit IFCONFIG.4 =1.
------------------ ----------- ---------- -----------------------------------------------------------------------
PE0 or
T0OUT on
CY7C68015A
I/O/Z
I
Multiplexed pin whose function is selected by the
(PE0) PORTECFG.0 bit.
PE0 is a bidirectional I/O port pin.
T0OUT is an active-HIGH signal from 8051
Timer-counter0. T0OUT outputs a high level for one
CLKOUT clock cycle when Timer0 overflows. If Timer0
is operated in Mode 3 (two separate timer/counters),
T0OUT is active when the low byte timer/counter
overflows.
28
106
31
22
84
25
INT4
INT5#
T2
Input
Input
Input
N/A INT4is the 8051 INT4 interruptrequestinput signal. The
INT4 pin is edge-sensitive, active HIGH.
N/A INT5# is the 8051 INT5 interrupt request input signal.
The INT5 pin is edge-sensitive, active LOW.
N/A T2 is the active-HIGH T2 input signal to 8051 Timer2,
which provides the input to Timer2 when C/T2 = 1.
When C/T2 = 0, Timer2 does not use this pin.
30
29
24
23
T1
T0
Input
Input
N/A T1 is the active-HIGH T1 signal for 8051 Timer1, which
provides the input to Timer1 when C/T1 is 1. When C/T1
is 0, Timer1 does not use this bit.
N/A T0 is the active-HIGH T0 signal for 8051 Timer0, which
provides the input to Timer0 when C/T0 is 1. When C/T0
is 0, Timer0 does not use this bit.
53
52
43
42
RXD1
TXD1
Input
N/A RXD1is an active-HIGH input signal for 8051 UART1,
which provides data to the UART in all modes.
Output
H
TXD1is an active-HIGH output pin from 8051 UART1,
which provides the output clock in sync mode, and the
output data in async mode.
Document #: 38-08032 Rev. *K
Page 27 of 60
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