CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
10.5
PORTC Strobe Feature Timings
The way the feature is intended to work is that the RD# signal
will prompt the external logic to prepare the next data byte.
Nothing gets sampled internally on assertion of the RD# signal
itself. It is just a “prefetch” type signal to get the next data byte
prepared. So, using it with that in mind should easily meet the
set-up time to the next read.
The purpose of this pulsing of RD# is to let the external
peripheral know that the 8051 is done reading PORTC and the
data was latched into PORTC three CLKOUT cycles prior to
asserting the RD# signal. Once the RD# is pulsed the external
logic may update the data on PORTC.
Following is the timing diagram of the read and write strobing
function on accessing PORTC. Refer to Section 10.3 and
signals.
The RD# and WR# are present in the 100-pin version and the
128-pin package. In these 100-pin and 128-pin versions, an
8051 control bit can be set to pulse the RD# and WR# pins
when the 8051 reads from/writes to PORTC. This feature is
enabled by setting PORTCSTB bit in CPUCS register.
The RD# and WR# strobes are asserted for two CLKOUT
cycles when PORTC is accessed.
The WR# strobe will be asserted two clock cycles after
PORTC is updated and will be active for two clock cycles after
that as shown in
As for read, the value of PORTC three clock cycles before the
assertion of RD# is the value that the 8051 reads in. The RD#
is pulsed for 2 clock cycles after 3 clock cycles from the point
when the 8051 has performed a read function on PORTC.
t
CLKOUT
CLKOUT
PORTC IS UPDATED
t
STBL
t
STBH
WR#
Figure 10-4. WR# Strobe Function when PORTC is Accessed by 8051
t
CLKOUT
CLKOUT
8051 READS PORTC
DATA MUST BE HELD FOR 3 CLK CYLCES
t
STBL
DATA CAN BE UPDATED BY EXTERNAL LOGIC
t
STBH
RD#
Figure 10-5. RD# Strobe Function when PORTC is Accessed by 8051
Document #: 38-08032 Rev. *K
Page 41 of 60
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