CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 5-1. FX2LP Register Summary (continued)
Hex Size Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default
Access
[11]
E6D1 1
GPIFTCB0
GPIF Transaction Count TC7
Byte 0
TC6
TC5
TC4
TC3
TC2
TC1
TC0
00000001 RW
2
reserved
reserved
reserved
00000000 RW
[11]
E6D2 1
E6D3 1
EP2GPIFFLGSEL
Endpoint 2 GPIF Flag
select
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1
0
FS0
00000000 RW
EP2GPIFPFSTOP Endpoint 2 GPIF stop
FIFO2FLAG 00000000 RW
transaction on prog. flag
[11]
E6D4 1
3
EP2GPIFTRIG
reserved
Endpoint 2 GPIF Trigger
x
x
xxxxxxxx
W
reserved
reserved
[11]
E6DA 1
E6DB 1
EP4GPIFFLGSEL
Endpoint 4 GPIF Flag
select
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1
0
FS0
00000000 RW
EP4GPIFPFSTOP Endpoint 4 GPIF stop
FIFO4FLAG 00000000 RW
transaction on GPIF Flag
[11]
E6DC 1
3
EP4GPIFTRIG
reserved
Endpoint 4 GPIF Trigger
x
x
xxxxxxxx
W
reserved
reserved
[11]
E6E2 1
E6E3 1
EP6GPIFFLGSEL
Endpoint 6 GPIF Flag
select
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1
0
FS0
00000000 RW
EP6GPIFPFSTOP Endpoint 6 GPIF stop
FIFO6FLAG 00000000 RW
transaction on prog. flag
[11]
E6E4 1
3
EP6GPIFTRIG
reserved
Endpoint 6 GPIF Trigger
x
x
xxxxxxxx
W
reserved
reserved
[11]
E6EA 1
E6EB 1
EP8GPIFFLGSEL
Endpoint 8 GPIF Flag
select
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1
0
FS0
00000000 RW
EP8GPIFPFSTOP Endpoint 8 GPIF stop
FIFO8FLAG 00000000 RW
transaction on prog. flag
[11]
E6EC 1
3
EP8GPIFTRIG
reserved
Endpoint 8 GPIF Trigger
x
x
xxxxxxxx
W
E6F0 1
XGPIFSGLDATH
GPIF Data H
D15
D14
D6
D13
D12
D4
D4
0
D11
D3
D3
0
D10
D2
D2
0
D9
D1
D1
0
D8
D0
D0
0
xxxxxxxx RW
xxxxxxxx RW
(16-bit mode only)
E6F1 1
E6F2 1
E6F3 1
XGPIFSGLDATLX
Read/WriteGPIF Data L& D7
trigger transaction
D5
XGPIFSGLDATL-
NOX
Read GPIF Data L, no
transaction trigger
D7
D6
D5
xxxxxxxx
R
GPIFREADYCFG
InternalRDY,Sync/Async, INTRDY
RDY pin states
SAS
TCXRDY5
00000000 bbbrrrrr
E6F4 1
E6F5 1
E6F6 2
GPIFREADYSTAT
GPIFABORT
GPIF Ready Status
0
x
0
x
RDY5
x
RDY4
x
RDY3
x
RDY2
x
RDY1
x
RDY0
x
00xxxxxx
xxxxxxxx
R
Abort GPIF Waveforms
W
reserved
ENDPOINT BUFFERS
E740 64 EP0BUF
E780 64 EP10UTBUF
E7C0 64 EP1INBUF
2048 reserved
EP0-IN/-OUT buffer
EP1-OUT buffer
EP1-IN buffer
D7
D7
D7
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
xxxxxxxx RW
xxxxxxxx RW
xxxxxxxx RW
RW
F000 1024 EP2FIFOBUF
512/1024-byte EP 2 /
slave FIFO buffer (IN or
OUT)
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx RW
F400 512 EP4FIFOBUF
512byteEP 4/slaveFIFO D7
buffer (IN or OUT)
xxxxxxxx RW
F600 512 reserved
F800 1024 EP6FIFOBUF
512/1024-byte EP 6 /
slave FIFO buffer (IN or
OUT)
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx RW
xxxxxxxx RW
FC00 512 EP8FIFOBUF
FE00 512 reserved
512byteEP 8/slaveFIFO D7
buffer (IN or OUT)
xxxx
I²C Configuration Byte
0
DISCON
0
0
0
0
0
400KHZ
xxxxxxxx n/a
[14]
Special Function Registers (SFRs)
[13]
80
81
82
83
84
85
1
1
1
1
1
1
IOA
SP
Port A (bit addressable) D7
D6
D5
D4
D3
D3
A3
D2
D1
D1
A1
A9
A1
A9
D0
D0
A0
A8
A0
A8
xxxxxxxx RW
00000111 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
Stack Pointer
D7
D6
D5
D4
D2
DPL0
DPH0
Data Pointer 0 L
Data Pointer 0 H
Data Pointer 1 L
Data Pointer 1 H
A7
A6
A5
A4
A2
A15
A7
A14
A6
A13
A5
A12
A4
A11
A3
A10
A2
[13]
DPL1
DPH1
[13]
A15
A14
A13
A12
A11
A10
Notes:
13. SFRs not part of the standard 8051 architecture.
14. If no EEPROM is detected by the SIE then the default is 00000000.
Document #: 38-08032 Rev. *G
Page 32 of 55
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