CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.3 Data Memory Read
Figure 9-2. Data Memory Read Timing Diagram
t
CL
Stretch = 0
CLKOUT
t
AV
A[15..0]
t
STBL
RD#
t
SCSL
CS#
t
SOEL
OE#
t
STBH
t
AV
D[7..0]
t
ACC1
t
DSU
data in
t
DH
t
CL
Stretch = 1
CLKOUT
t
AV
A[15..0]
RD#
CS#
t
DSU
data in
D[7..0]
t
ACC1
t
DH
Table 15. Data Memory Read Parameters
Parameter
t
CL
Description
1/CLKOUT frequency
Min
–
–
–
t
AV
t
STBL
t
STBH
t
SCSL
t
SOEL
t
DSU
t
DH
Delay from clock to valid address
Clock to RD LOW
Clock to RD HIGH
Clock to CS LOW
Clock to OE LOW
Data setup to clock
Data hold time
–
–
–
–
–
9.6
0
Typ
20.83
41.66
83.2
–
–
–
–
–
–
–
Max
–
–
–
10.7
11
11
13
11.1
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
48 MHz
24 MHz
12 MHz
–
–
–
–
–
–
–
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either
RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which
is based on the stretch value
Note
19. t
ACC2
and t
ACC3
are computed from these parameters as follows:
t
ACC2
(24 MHz) = 3*t
CL
– t
AV
–t
DSU
= 106 ns.
t
ACC2
(48 MHz) = 3*t
CL
– t
AV
– t
DSU
= 43 ns.
t
ACC3
(24 MHz) = 5*t
CL
– t
AV
–t
DSU
= 190 ns.
t
ACC3
(48 MHz) = 5*t
CL
– t
AV
– t
DSU
= 86 ns.
Document #: 38-08032 Rev. *V
Page 40 of 66
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