CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 11. FX2LP Register Summary
(continued)
Hex Size
Name
xxxx
I²C Configuration Byte
Description
0
b7
b6
DISCON
b5
0
0
b4
0
b3
0
b2
0
b1
b0
400KHZ
Default Access
xxxxxxxx n/a
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A8
A9
AA
AB
AC
AD
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
1
1
1
1
1
1
1
1
1
1
1
5
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Special Function Registers (SFRs)
IOA
Port A (bit addressable)
SP
Stack Pointer
DPL0
Data Pointer 0 L
DPH0
Data Pointer 0 H
DPL1
Data Pointer 1 L
DPH1
Data Pointer 1 H
DPS
Data Pointer 0/1 select
PCON
Power Control
TCON
Timer/Counter Control
(bit addressable)
TMOD
Timer/Counter Mode
Control
TL0
Timer 0 reload L
TL1
Timer 1 reload L
TH0
Timer 0 reload H
TH1
Timer 1 reload H
CKCON
Clock Control
reserved
IOB
Port B (bit addressable)
EXIF
External Interrupt Flag(s)
MPAGE
Upper Addr Byte of MOVX
using @R0 / @R1
reserved
SCON0
Serial Port 0 Control
(bit addressable)
SBUF0
Serial Port 0 Data Buffer
AUTOPTRH1
Autopointer 1 Address H
AUTOPTRL1
Autopointer 1 Address L
reserved
AUTOPTRH2
Autopointer 2 Address H
AUTOPTRL2
Autopointer 2 Address L
reserved
IOC
Port C (bit addressable)
INT2CLR
Interrupt 2 clear
INT4CLR
Interrupt 4 clear
reserved
IE
Interrupt Enable
(bit addressable)
reserved
EP2468STAT
Endpoint 2,4,6,8 status
flags
EP24FIFOFLGS
Endpoint 2,4 slave FIFO
status flags
EP68FIFOFLGS
Endpoint 6,8 slave FIFO
status flags
reserved
AUTOPTRSETUP
Autopointer 1&2 setup
IOD
Port D (bit addressable)
IOE
Port E
(NOT bit addressable)
OEA
Port A Output Enable
OEB
Port B Output Enable
OEC
Port C Output Enable
OED
Port D Output Enable
OEE
Port E Output Enable
reserved
IP
Interrupt Priority (bit ad-
dressable)
reserved
EP01STAT
Endpoint 0&1 Status
GPIFTRIG
Endpoint 2,4,6,8 GPIF
slave FIFO Trigger
reserved
GPIFSGLDATH
GPIF Data H (16-bit mode
only)
D7
D7
A7
A15
A7
A15
0
SMOD0
TF1
GATE
D7
D7
D15
D15
x
D7
IE5
A15
D6
D6
A6
A14
A6
A14
0
x
TR1
CT
D6
D6
D14
D14
x
D6
IE4
A14
D5
D5
A5
A13
A5
A13
0
1
TF0
M1
D5
D5
D13
D13
T2M
D5
I²CINT
A13
D4
D4
A4
A12
A4
A12
0
1
TR0
M0
D4
D4
D12
D12
T1M
D4
USBNT
A12
D3
D3
A3
A11
A3
A11
0
x
IE1
GATE
D3
D3
D11
D11
T0M
D3
1
A11
D2
D2
A2
A10
A2
A10
0
x
IT1
CT
D2
D2
D10
D10
MD2
D2
0
A10
D1
D1
A1
A9
A1
A9
0
x
IE0
M1
D1
D1
D9
D9
MD1
D1
0
A9
D0
D0
A0
A8
A0
A8
SEL
IDLE
IT0
M0
D0
D0
D8
D8
MD0
D0
0
A8
xxxxxxxx
00000111
00000000
00000000
00000000
00000000
00000000
00110000
00000000
RW
RW
RW
RW
RW
RW
RW
RW
RW
00000000 RW
00000000
00000000
00000000
00000000
00000001
RW
RW
RW
RW
RW
xxxxxxxx RW
00001000 RW
00000000 RW
SM0_0
D7
A15
A7
A15
A7
D7
x
x
EA
SM1_0
D6
A14
A6
A14
A6
D6
x
x
ES1
SM2_0
D5
A13
A5
A13
A5
D5
x
x
ET2
REN_0
D4
A12
A4
A12
A4
D4
x
x
ES0
TB8_0
D3
A11
A3
A11
A3
D3
x
x
ET1
RB8_0
D2
A10
A2
A10
A2
D2
x
x
EX1
TI_0
D1
A9
A1
A9
A1
D1
x
x
ET0
RI_0
D0
A8
A0
A8
A0
D0
x
x
EX0
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
xxxxxxxx RW
xxxxxxxx W
xxxxxxxx W
00000000 RW
EP8F
0
0
EP8E
EP4PF
EP8PF
EP6F
EP4EF
EP8EF
EP6E
EP4FF
EP8FF
EP4F
0
0
EP4E
EP2PF
EP6PF
EP2F
EP2EF
EP6EF
EP2E
EP2FF
EP6FF
01011010 R
00100010 R
01100110 R
0
D7
D7
D7
D7
D7
D7
D7
1
0
D6
D6
D6
D6
D6
D6
D6
PS1
0
D5
D5
D5
D5
D5
D5
D5
PT2
0
D4
D4
D4
D4
D4
D4
D4
PS0
0
D3
D3
D3
D3
D3
D3
D3
PT1
APTR2INC
D2
D2
D2
D2
D2
D2
D2
PX1
APTR1INC
D1
D1
D1
D1
D1
D1
D1
PT0
APTREN
D0
D0
D0
D0
D0
D0
D0
PX0
00000110 RW
xxxxxxxx RW
xxxxxxxx RW
00000000
00000000
00000000
00000000
00000000
RW
RW
RW
RW
RW
10000000 RW
0
DONE
0
0
0
0
0
0
0
0
EP1INBSY
RW
EP1OUTBSY EP0BSY
EP1
EP0
00000000 R
10000xxx brrrrbbb
D15
D14
D13
D12
D11
D10
D9
D8
xxxxxxxx RW
Notes
13. SFRs not part of the standard 8051 architecture.
14. If no EEPROM is detected by the SIE then the default is 00000000.
Document #: 38-08032 Rev. *V
Page 35 of 66
CYPRESS [ CYPRESS SEMICONDUCTOR ]
