CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
4. Register Summary
FX2LP register bit definitions are described in the FX2LP TRM in greater detail.
Table 11. FX2LP Register Summary
Name
Description
GPIF Waveform Memories
E400 128 WAVEDATA
GPIF Waveform
Descriptor 0, 1, 2, 3 data
E480 128 reserved
GENERAL CONFIGURATION
E50D
GPCR2
General Purpose Configu-
ration Register 2
E600 1
CPUCS
CPU Control & Status
E601 1
IFCONFIG
Interface Configuration
(Ports, GPIF, slave FIFOs)
E602 1
PINFLAGSAB
Slave FIFO FLAGA and
FLAGB Pin Configuration
E603 1
PINFLAGSCD
Slave FIFO FLAGC and
FLAGD Pin Configuration
E604 1
FIFORESET
Restore FIFOS to default
state
E605 1
BREAKPT
Breakpoint Control
E606 1
BPADDRH
Breakpoint Address H
E607 1
BPADDRL
Breakpoint Address L
E608 1
UART230
230 Kbaud internally
generated ref. clock
E609 1
FIFOPINPOLAR
Slave FIFO Interface pins
polarity
E60A 1
REVID
Chip Revision
E60B 1
E60C 1
3
E610 1
E611 1
E612
E613
E614
E615
1
1
1
1
2
E618 1
E619 1
E61A 1
E61B 1
E61C 4
E620 1
E621 1
E622 1
E623 1
E624 1
E625 1
E626 1
E627 1
E628 1
E629 1
E62A 1
REVCTL
Chip Revision Control
UDMA
GPIFHOLDAMOUNT MSTB Hold Time
(for UDMA)
reserved
ENDPOINT CONFIGURATION
EP1OUTCFG
Endpoint 1-OUT
Configuration
EP1INCFG
Endpoint 1-IN
Configuration
EP2CFG
Endpoint 2 Configuration
EP4CFG
Endpoint 4 Configuration
EP6CFG
Endpoint 6 Configuration
EP8CFG
Endpoint 8 Configuration
reserved
EP2FIFOCFG
Endpoint 2 / slave FIFO
configuration
EP4FIFOCFG
Endpoint 4 / slave FIFO
configuration
EP6FIFOCFG
Endpoint 6 / slave FIFO
configuration
EP8FIFOCFG
Endpoint 8 / slave FIFO
configuration
reserved
EP2AUTOINLENH
Endpoint 2 AUTOIN
Packet Length H
EP2AUTOINLENL
Endpoint 2 AUTOIN
Packet Length L
EP4AUTOINLENH
Endpoint 4 AUTOIN
Packet Length H
EP4AUTOINLENL
Endpoint 4 AUTOIN
Packet Length L
EP6AUTOINLENH
Endpoint 6 AUTOIN
Packet Length H
EP6AUTOINLENL
Endpoint 6 AUTOIN
Packet Length L
EP8AUTOINLENH
Endpoint 8 AUTOIN
Packet Length H
EP8AUTOINLENL
Endpoint 8 AUTOIN
Packet Length L
ECCCFG
ECC Configuration
ECCRESET
ECC Reset
ECC1B0
ECC1 Byte 0 Address
Hex Size
b7
D7
D6
b6
D5
b5
D4
b4
D3
b3
D2
b2
D1
b1
D0
b0
Default
Access
xxxxxxxx RW
reserved
0
IFCLKSRC
FLAGB3
FLAGD3
NAKALL
0
A15
A7
0
0
rv7
0
0
reserved
0
3048MHZ
FLAGB2
FLAGD2
0
0
A14
A6
0
0
rv6
0
0
reserved
FULL_SPEE reserved
D_ONLY
PORTCSTB CLKSPD1
CLKSPD0
IFCLKOE
IFCLKPOL ASYNC
FLAGB1
FLAGD1
0
0
A13
A5
0
PKTEND
rv5
0
0
FLAGB0
FLAGD0
0
0
A12
A4
0
SLOE
rv4
0
0
FLAGA3
FLAGC3
EP3
BREAK
A11
A3
0
SLRD
rv3
0
0
reserved
CLKINV
GSTATE
FLAGA2
FLAGC2
EP2
BPPULSE
A10
A2
0
SLWR
rv2
0
0
reserved
CLKOE
IFCFG1
FLAGA1
FLAGC1
EP1
BPEN
A9
A1
230UART1
EF
rv1
dyn_out
reserved
8051RES
IFCFG0
FLAGA0
FLAGC0
EP0
0
A8
A0
230UART0
FF
rv0
enh_pkt
00000000 R
00000010 rrbbbbbr
10000000 RW
00000000 RW
00000000 RW
xxxxxxxx W
00000000
xxxxxxxx
xxxxxxxx
00000000
rrrrbbbr
RW
RW
rrrrrrbb
00000000 rrbbbbbb
RevA
R
00000001
00000000 rrrrrrbb
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
VALID
VALID
VALID
VALID
VALID
VALID
0
0
0
0
0
0
DIR
DIR
DIR
DIR
INFM1
INFM1
INFM1
INFM1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
OEP1
OEP1
OEP1
OEP1
TYPE0
TYPE0
TYPE0
TYPE0
TYPE0
TYPE0
AUTOOUT
AUTOOUT
AUTOOUT
AUTOOUT
0
0
SIZE
0
SIZE
0
AUTOIN
AUTOIN
AUTOIN
AUTOIN
0
0
0
0
0
0
0
0
BUF1
0
BUF1
0
0
0
BUF0
0
BUF0
0
10100000 brbbrrrr
10100000 brbbrrrr
10100010
10100000
11100010
11100000
bbbbbrbb
bbbbrrrr
bbbbbrbb
bbbbrrrr
ZEROLENIN 0
ZEROLENIN 0
ZEROLENIN 0
ZEROLENIN 0
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
0
PL7
0
PL7
0
PL7
0
PL7
0
x
LINE15
0
PL6
0
PL6
0
PL6
0
PL6
0
x
LINE14
0
PL5
0
PL5
0
PL5
0
PL5
0
x
LINE13
0
PL4
0
PL4
0
PL4
0
PL4
0
x
LINE12
0
PL3
0
PL3
0
PL3
0
PL3
0
x
LINE11
PL10
PL2
0
PL2
PL10
PL2
0
PL2
0
x
LINE10
PL9
PL1
PL9
PL1
PL9
PL1
PL9
PL1
0
x
LINE9
PL8
PL0
PL8
PL0
PL8
PL0
PL8
PL0
ECCM
x
LINE8
00000010 rrrrrbbb
00000000 RW
00000010 rrrrrrbb
00000000 RW
00000010 rrrrrbbb
00000000 RW
00000010 rrrrrrbb
00000000 RW
00000000 rrrrrrrb
00000000 W
00000000 R
Note
11. Read and writes to these registers may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”
Document #: 38-08032 Rev. *V
Page 30 of 66
CYPRESS [ CYPRESS SEMICONDUCTOR ]
