CY7C68013A-56LTXCT 参数 Datasheet PDF下载

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

3.1 CY7C68013A/15A Pin Descriptions

The FX2LP pin descriptions follow.

Table 10. FX2LP Pin Descriptions

128 100

56

56

56

TQFP TQFP SSOP QFN VFBGA

10

9

10

3

2D

Name

AVCC

Type

Power

Default

N/A

Description

Analog VCC.

Connect this pin to 3.3V power source.

This signal provides power to the analog section of the

chip.

Analog VCC.

Connect this pin to 3.3V power source.

This signal provides power to the analog section of the

chip.

Analog Ground.

Connect to ground with as short a path

as possible.

Analog Ground.

Connect to ground with as short a path

as possible.

USB D– Signal.

Connect to the USB D– signal.

USB D+ Signal.

Connect to the USB D+ signal.

8051 Address Bus.

This bus is driven at all times.

When the 8051 is addressing internal RAM it reflects

the internal address.

17

16

14

7

1D

AVCC

Power

N/A

13

20

19

18

94

95

96

97

–

–

–

–

12

19

18

17

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

13

17

16

15

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

6

10

9

8

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

2F

1F

1E

2E

AGND

AGND

DMINUS

DPLUS

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

D0

D1

D2

D3

D4

D5

D6

D7

PSEN#

Ground

Ground

I/O/Z

I/O/Z

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

Output

N/A

N/A

Z

Z

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

Z

Z

Z

Z

Z

Z

Z

Z

H

117 –

118 –

119 –

120 –

126 –

127 –

128 –

21

22

23

24

25

59

60

61

62

63

86

87

88

39

–

–

–

–

–

–

–

–

–

–

–

–

–

–

8051 Data Bus.

This bidirectional bus is high

impedance when inactive, input for bus reads, and

output for bus writes. The data bus is used for external

8051 program and data memory. The data bus is active

only for external bus accesses, and is driven LOW in

suspend.

Program Store Enable.

This active-LOW signal

indicates an 8051 code fetch from external memory. It

is active for program memory fetches from

0x4000–0xFFFF when the EA pin is LOW, or from

0x0000–0xFFFF when the EA pin is HIGH.

Note

10. Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in

standby. Note also that no pins should be driven while the device is powered down.

Document #: 38-08032 Rev. *V

Page 22 of 66