CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 3-4. Individual FIFO/GPIF Interrupt Sources
Priority
INT4VEC Value
Source
EP2PF
EP4PF
EP6PF
EP8PF
EP2EF
EP4EF
EP6EF
EP8EF
EP2FF
EP4FF
EP6FF
EP8FF
GPIFDONE
GPIFWF
Notes
1
2
80
84
88
8C
90
94
98
9C
A0
A4
A8
AC
B0
B4
Endpoint 2 Programmable Flag
Endpoint 4 Programmable Flag
Endpoint 6 Programmable Flag
Endpoint 8 Programmable Flag
Endpoint 2 Empty Flag
Endpoint 4 Empty Flag
Endpoint 6 Empty Flag
Endpoint 8 Empty Flag
Endpoint 2 Full Flag
3
4
5
6
7
8
9
10
11
12
13
14
Endpoint 4 Full Flag
Endpoint 6 Full Flag
Endpoint 8 Full Flag
GPIF Operation Complete
GPIF Waveform
If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP
register), the FX 2LP substitutes its INT4VEC byte. Therefore,
if the high byte (“page”) of a jump-table address is preloaded
at location 0x0054, the automatically-inserted INT4VEC byte
at 0x0055 will direct the jump to the correct address out of the
14 addresses within the page. When the ISR occurs, the
FX2LP pushes the program counter onto its stack then jumps
to address 0x0053, where it expects to find a “jump” instruction
to the ISR Interrupt service routine.
used with the CY7C680xxA the reset period must allow for the
stabilization of the crystal and the PLL. This reset period
should be approximately 5 ms after VCC has reached 3.0V. If
the crystal input pin is driven by a clock signal the internal PLL
[3]
stabilizes in 200 µs after VCC has reached 3.0V . Figure 3-2
shows a power-on reset condition and a reset applied during
operation. A power-on reset is defined as the time reset is
asserted while power is being applied to the circuit. A powered
reset is defined to be when the FX2LP has previously been
powered on and operating and the RESET# pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation and can be found
on the Cypress web site. For more information on reset imple-
mentation for the FX2 family of products visit the
http://www.cypress.com.
3.9
Reset and Wakeup
3.9.1
Reset Pin
The input pin, RESET#, will reset the FX2LP when asserted.
This pin has hysteresis and is active LOW. When a crystal is
Note:
3. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 µs.
Document #: 38-08032 Rev. *G
Page 6 of 55
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