CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
an easy and glueless interface to popular interfaces such as
ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors.
1.2
Features (CY7C68015A/16A only)
• CY7C68016A: Ideal for battery powered applications
The FX2LP draws considerably less current than the FX2
(CY7C68013), has double the on-chip code/data RAM and is
fit, form and function compatible with the 56-, 100-, and 128-
pin FX2.
— Suspend current: 100 µA (typ)
• CY7C68015A: Ideal for non-battery powered applica-
tions
— Suspend current: 300 µA (typ)
• Available in lead-free 56-pin QFN package (26 GPIOs)
Four packages are defined for the family: 56 SSOP, 56 QFN,
100 TQFP, and 128 TQFP.
— 2 more GPIOs than CY7C68013A/14A enabling addi-
tional features in same footprint
2.0
Applications
• Portable video recorder
• MPEG/TV conversion
• DSL modems
Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB
FX2LP (CY7C68013A/14A) is a low-power version of the
EZ-USB FX2 (CY7C68013), which is a highly integrated,
low-power USB 2.0 microcontroller. By integrating the USB 2.0
transceiver, serial interface engine (SIE), enhanced 8051
microcontroller, and a programmable peripheral interface in a
single chip, Cypress has created a very cost-effective solution
that provides superior time-to-market advantages with low
power to enable bus powered applications.
• ATA interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
The ingenious architecture of FX2LP results in data transfer
rates of over 53 Mbytes per second, the maximum-allowable
USB 2.0 bandwidth, while still using a low-cost 8051 microcon-
troller in a package as small as a 56 QFN. Because it incorpo-
rates the USB 2.0 transceiver, the FX2LP is more economical,
providing a smaller footprint solution than USB 2.0 SIE or
external transceiver implementations. With EZ-USB FX2LP,
the Cypress Smart SIE handles most of the USB 1.1 and 2.0
protocol in hardware, freeing the embedded microcontroller for
application-specific functions and decreasing development
time to ensure USB compatibility.
• Home PNA
• Wireless LAN
• MP3 players
• Networking
The “Reference Designs” section of the Cypress web site
provides additional tools for typical USB 2.0 applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. Please visit
http://www.cypress.com for more information.
The General Programmable Interface (GPIF) and
Master/Slave Endpoint FIFO (8- or 16-bit data bus) provides
Document #: 38-08032 Rev. *G
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