CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
3.13.3
GPIF and FIFO Clock Rates
3.15
ECC Generation
An 8051 register bit selects one of two frequencies for the
internally supplied interface clock: 30 MHz and 48 MHz. Alter-
natively, an externally supplied clock of 5 MHz–48 MHz
feeding the IFCLK pin can be used as the interface clock.
IFCLK can be configured to function as an output clock when
the GPIF and FIFOs are internally clocked. An output enable
bit in the IFCONFIG register turns this clock output off, if
desired. Another bit within the IFCONFIG register will invert
the IFCLK signal whether internally or externally sourced.
The EZ-USB can calculate ECCs (Error-Correcting Codes) on
data that passes across its GPIF or Slave FIFO interfaces.
There are two ECC configurations: Two ECCs, each calcu-
lated over 256 bytes (SmartMedia™ Standard); and one ECC
calculated over 512 bytes.
The ECC can correct any one-bit error or detect any two-bit
error.
3.15.1
ECC Implementation
3.14
GPIF
The two ECC configurations are selected by the ECCM bit:
3.15.1.1 ECCM=0
Two 3-byte ECCs, each calculated over a 256-byte block of
data. This configuration conforms to the SmartMedia
Standard.
Write any value to ECCRESET, then pass data across the
GPIF or Slave FIFO interface. The ECC for the first 256 bytes
of data will be calculated and stored in ECC1. The ECC for the
next 256 bytes will be stored in ECC2. After the second ECC
is calculated, the values in the ECCx registers will not change
until ECCRESET is written again, even if more data is subse-
quently passed across the interface.
3.15.1.2 ECCM=1
One 3-byte ECC calculated over a 512-byte block of data.
Write any value to ECCRESET then pass data across the
GPIF or Slave FIFO interface. The ECC for the first 512 bytes
of data will be calculated and stored in ECC1; ECC2 is unused.
After the ECC is calculated, the value in ECC1 will not change
until ECCRESET is written again, even if more data is subse-
quently passed across the interface
The GPIF is a flexible 8- or 16-bit parallel interface driven by a
user-programmable finite state machine. It allows the
CY7C68013A/15A to perform local bus mastering, and can
implement a wide variety of protocols such as ATA interface,
printer parallel port, and Utopia.
The GPIF has six programmable control outputs (CTL), nine
address outputs (GPIFADRx), and six general-purpose ready
inputs (RDY). The data bus width can be 8 or 16 bits. Each
GPIF vector defines the state of the control outputs, and deter-
mines what state a ready input (or multiple inputs) must be
before proceeding. The GPIF vector can be programmed to
advance a FIFO to the next data value, advance an address,
etc. A sequence of the GPIF vectors make up a single
waveform that will be executed to perform the desired data
move between the FX2LP and the external device.
3.14.1
Six Control OUT Signals
The 100- and 128-pin packages bring out all six Control Output
pins (CTL0-CTL5). The 8051 programs the GPIF unit to define
the CTL waveforms. The 56-pin package brings out three of
these signals, CTL0–CTL2. CTLx waveform edges can be
programmed to make transitions as fast as once per clock
(20.8 ns using a 48-MHz clock).
3.14.2
Six Ready IN Signals
3.16
USB Uploads and Downloads
The 100- and 128-pin packages bring out all six Ready inputs
(RDY0–RDY5). The 8051 programs the GPIF unit to test the
RDY pins for GPIF branching. The 56-pin package brings out
two of these signals, RDY0–1.
3.14.3
Nine GPIF Address OUT Signals
The core has the ability to directly edit the data contents of the
internal 16-KByte RAM and of the internal 512-byte scratch
pad RAM via a vendor-specific command. This capability is
normally used when “soft” downloading user code and is
available only to and from internal RAM, only when the 8051
is held in reset. The available RAM spaces are 16 KBytes from
0x0000–0x3FFF (code/data) and 512 bytes from
0xE000–0xE1FF (scratch pad data RAM).
Nine GPIF address lines are available in the 100- and 128-pin
packages, GPIFADR[8..0]. The GPIF address lines allow
indexing through up to a 512-byte block of RAM. If more
address lines are needed, I/O port pins can be used.
3.14.4
Long Transfer Mode
3.17
Autopointer Access
In master mode, the 8051 appropriately sets GPIF transaction
count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
GPIFTCB0) for unattended transfers of up to 2
32
transactions.
The GPIF automatically throttles data flow to prevent under or
overflow until the full number of requested transactions
complete. The GPIF decrements the value in these registers
to represent the current status of the transaction.
FX2LP provides two identical autopointers. They are similar to
the internal 8051 data pointers, but with an additional feature:
they can optionally increment after every memory access. This
capability is available to and from both internal and external
RAM. The autopointers are available in external FX2LP
registers, under control of a mode bit (AUTOPTRSET-UP.0).
Using the external FX2LP autopointer access (at 0xE67B –
0xE67C) allows the autopointer to access all RAM, internal
and external to the part. Also, the autopointers can point to any
FX2LP register or endpoint buffer space. When autopointer
access to external memory is enabled, location 0xE67B and
0xE67C in XDATA and code space cannot be used.
Notes:
7. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
8. After the data has been downloaded from the host, a “loader” can execute from internal RAM in order to transfer downloaded data to external memory.
Document #: 38-08032 Rev. *G
Page 12 of 55
CYPRESS [ CYPRESS SEMICONDUCTOR ]
