CY7C64713/14
until ECCRESET is written again, even if more data is subse-
quently passed across the interface
4.18.2
I
2
C Interface Boot Load Access
At power-on reset the I
2
C interface boot loader will load the
VID/PID/DID configuration bytes and up to 16 KBytes of
program/data. The available RAM spaces are 16 KBytes from
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The
8051 will be in reset. I
2
C interface boot loads only occur after
power-on reset.
4.18.3
I
2
C Interface General Purpose Access
4.16
USB Uploads and Downloads
The core has the ability to directly edit the data contents of the
internal 16 KByte RAM and of the internal 512-byte scratch
pad RAM via a vendor-specific command. This capability is
normally used when “soft” downloading user code and is
available only to and from internal RAM, only when the 8051
is held in reset. The available RAM spaces are 16 KBytes from
0x0000–0x3FFF (code/data) and 512 bytes from
0xE000–0xE1FF (scratch pad data RAM).
[6]
The 8051 can control peripherals connected to the I
2
C bus
using the I2CTL and I2DAT registers. FX1 provides I
2
C master
control only, it is never an I
2
C slave.
4.17
Autopointer Access
FX1 provides two identical autopointers. They are similar to
the internal 8051 data pointers, but with an additional feature:
they can optionally increment after every memory access. This
capability is available to and from both internal and external
RAM. The autopointers are available in external FX1 registers,
under control of a mode bit (AUTOPTRSETUP.0). Using the
external FX1 autopointer access (at 0xE67B – 0xE67C) allows
the autopointer to access all RAM, internal and external to the
part. Also, the autopointers can point to any FX1 register or
endpoint buffer space. When autopointer access to external
memory is enabled, location 0xE67B and 0xE67C in XDATA
and code space cannot be used.
4.19
Compatible with Previous Generation
EZ-USB FX2
The EZ-USB FX1 is fit/form/function-upgradable to the EZ-
USB FX2LP. This makes for a easy transition for designers
wanting to upgrade their systems from full-speed to the high-
speed designs. The pinout and package selection are
identical, and all of the firmware developed for the FX1 will
function in the FX2LP with proper addition of High Speed
descriptors and speed switching code.
5.0
Pin Assignments
4.18
I
2
C Controller
FX1 has one I
2
C port that is driven by two internal controllers,
one that automatically operates at boot time to load
VID/PID/DID and configuration information, and another that
the 8051, once running, uses to control external I
2
C devices.
The I
2
C port operates in master mode only.
4.18.1
I
2
C Port Pins
Figure 5-1
identifies all signals for the three package types.
The following pages illustrate the individual pin diagrams, plus
a combination diagram showing which of the full set of signals
are available in the 128-, 100-, and 56-pin packages.
The signals on the left edge of the 56-pin package in
Figure 5-
1
are common to all versions in the FX1 family. Three modes
are available in all package versions: Port, GPIF master, and
Slave FIFO. These modes define the signals on the right edge
of the diagram. The 8051 selects the interface mode using the
IFCONFIG[1:0] register bits. Port mode is the power-on default
configuration.
The 100-pin package adds functionality to the 56-pin package
by adding these pins:
• PORTC or alternate GPIFADR[7:0] address signals
• PORTE or alternate GPIFADR[8] address signal and seven
additional 8051 signals
• Three GPIF Control signals
• Four GPIF Ready signals
• Nine 8051 signals (two USARTs, three timer inputs,
INT4,and INT5#)
• BKPT, RD#, WR#.
The 128-pin package adds the 8051 address and data buses
plus control signals. Note that two of the required signals, RD#
and WR#, are present in the 100-pin version. In the 100-pin
and 128-pin versions, an 8051 control bit can be set to pulse
the RD# and WR# pins when the 8051 reads from/writes to
PORTC.
The I
2
C- pins SCL and SDA must have external 2.2-kΩ pull-
up resistors even if no EEPROM is connected to the FX1.
External EEPROM device address pins must be configured
properly. See
Table 4-7
for configuring the device address
pins.
Table 4-7. Strap Boot EEPROM Address Lines to These
Values
Bytes
16
128
256
4K
8K
16K
Example EEPROM
24LC00
[7]
A2
N/A
0
0
0
0
0
A1
N/A
0
0
0
0
0
A0
N/A
0
0
1
1
1
24LC01
24LC02
24LC32
24LC64
24LC128
Notes:
6. After the data has been downloaded from the host, a “loader” can execute from internal RAM in order to transfer downloaded data to external memory.
7. This EEPROM does not have address pins.
Document #: 38-08039 Rev. *B
Page 11 of 50
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