FOR
FOR
CY7C63411/12/13
CY7C63511/12/13
CY7C63612/13
.
Logic Block Diagram
Pin Configuration
6-MHz ceramic resonator
48-pin SSOP
48-pin SideBraze
48-pin SSOP
48-pin SideBraze
D+
1
2
3
4
48
47
46
VCC
Vss
D+
1
2
3
4
48
47
46
VCC
Vss
OSC
D–
P3[7]
P3[5]
P3[3]
P3[1]
P2[7]
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]
DAC[7]
DAC[5]
P0[7]
P0[5]
P0[3]
P0[1]
DAC[3]
DAC[1]
VPP
D–
P3[7]
P3[5]
P3[3]
P3[1]
P2[7]
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]
NC
P3[6]
P3[4]
P3[2]
P3[0]
P2[6]
P2[4]
P3[6]
P3[4]
P3[2]
P3[0]
P2[6]
P2[4]
12 MHz 6 MHz
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
5
6
7
8
5
6
7
8
12-MHz
8-bit
CPU
USB
PS/2
PORT
USB
Transceiver
D+
D–
9
P2[2]
P2[0]
P1[6]
P1[4]
P1[2]
P1[0]
DAC[6]
DAC[4]
P0[6]
P0[4]
P0[2]
P0[0]
DAC[2]
DAC[0]
XTALOUT
XTALIN
9
P2[2]
P2[0]
P1[6]
P1[4]
P1[2]
P1[0]
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
USB
SIE
EPROM
4/6/8 Kbyte
NC
NC
P0[7]
P0[5]
P0[3]
P0[1]
NC
NC
VPP
Vss
P0[6]
P0[4]
P0[2]
P0[0]
NC
NC
XTALOUT
XTALIN
RAM
256 byte
Interrupt
Controller
Vss
See Note 1
TOP VIEW
P0[0]
12-bit
Timer
GPIO
PORT 0
CY7C63411/12/13
40-pin PDIP
40-pin CerDIP
P0[7]
CY7C63612/13
24-pin SOIC
D+
1
40 VCC
P1[0]
P1[7]
GPIO
PORT 1
D–
P3[7]
P3[5]
P3[3]
P3[1]
P2[7]
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]
P0[7]
P0[5]
P0[3]
P0[1]
VPP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39 VSS
38 P3[6]
37 P3[4]
36 P3[2]
35 P3[0]
34 P2[6]
33 P2[4]
32 P2[2]
31 P2[0]
30 P1[6]
29 P1[4]
D+
1
24
VCC
D–
P3[7]
P3[5]
P1[3]
P1[1]
P0[7]
P0[5]
P0[3]
P0[1]
VPP
2
3
4
5
6
7
8
9
23
22
21
20
19
18
17
16
15
14
13
VSS
P3[6]
P3[4]
P1[2]
P1[0]
P0[6]
P0[4]
P0[2]
P0[0]
XTALOUT
XTALIN
P2[0]
P2[7]
GPIO
PORT 2
Watch Dog
Timer
28
27
26
25
24
23
22
21
P1[2]
P1[0]
P0[6]
P0[4]
P0[2]
P0[0]
XTALOUT
XTALIN
P3[0]
10
11
12
GPIO
PORT 3
High Current
Outputs
Vss
P3[7]
TOP VIEW
DAC[0]
DAC[7]
Power-on
Reset
DAC
PORT
Vss
TOP VIEW
Note:
1. CY7C63612/13 is not bonded out for all GPIO pins shown in Logic Block Diagram. Refer to pin configuration diagram for bonded out pins. See note on page 17
for firmware code needed for unused GPIO pins.
Document #: 38-08027 Rev. **
Page 7 of 36
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