CY7C63001A
CY7C63101A
6.8.2
GPIO Interrupt
The General Purpose I/O interrupts are generated by signal
transitions at the Port 0 and Port 1 I/O pins. GPIO interrupts
are edge sensitive with programmable interrupt polarities.
Setting a bit HIGH in the Port Pull-up Register (see
and
selects a LOW to HIGH interrupt trigger for the
corresponding port pin. Setting a bit LOW activates a HIGH to
b7
IE0.7
W
0
b6
IE0.6
W
0
b5
IE0.5
W
0
b4
IE0.4
W
0
LOW interrupt trigger. Each GPIO interrupt is maskable on a
per-pin basis by a dedicated bit in the Port Interrupt Enable
Register. Writing a “1” enables the interrupt.
and
illustrate the format of the Port Interrupt Enable
Registers for Port 0 and Port 1 located at I/O address 0x04 and
0x05 respectively. These write only registers are cleared
during reset, thus disabling all GPIO interrupts.
b3
IE0.3
W
0
b2
IE0.2
W
0
b1
IE0.1
W
0
b0
IE0.0
W
0
Figure 6-17. Port 0 Interrupt Enable Register (P0 IE – Address 0x04)
b7
IE1.7
W
0
b6
IE1.6
W
0
b5
IE1.5
W
0
b4
IE1.4
W
0
b3
IE1.3
W
0
b2
IE1.2
W
0
b1
IE1.1
W
0
b0
IE1.0
W
0
Figure 6-18. Port 1 Interrupt Enable Register (P1 IE – Address 0x05)
A block diagram of the GPIO interrupt logic is shown in
The bit setting in the Port Pull-up Register selects the
interrupt polarity. If the selected signal polarity is detected on
the I/O pin, a HIGH signal is generated. If the Port Interrupt
Enable bit for this pin is HIGH and no other port pins are
requesting interrupts, the OR gate issues a LOW to HIGH
Port
Pull-Up
Register
1=L
→
H
0=H
Æ
L
signal to clock the GPIO interrupt flip-flop. The output of the
flip-flop is further qualified by the Global GPIO Interrupt Enable
bit before it is processed by the Interrupt Priority Encoder. Both
the GPIO interrupt flip-flop and the Global GPIO Enable bit are
cleared by on-chip hardware during GPIO interrupt
acknowledge.
GPIO Interrupt
Flip-Flop
I
D
Q
OR Gate
(1 input per
GPIO pin)
GPIO
Pin
M
U
X
CLR
1 = Enable
0 = Disable
Port Interrupt
Enable Register
Interrupt
Acknowledge
CLR
Global
1 = Enable
GPIO Interrupt
0 = Disable
Enable
(Bit 6, Register 0x20)
Interrupt
Priority
Encoder
IRQ
Interrupt
Vector
Figure 6-19. GPIO Interrupt Logic Block Diagram
Note.
If one port pin triggers an interrupt, no other port pin can
cause a GPIO interrupt until the port pin that triggered the
interrupt has returned to its inactive (non-trigger) state or until
its corresponding port interrupt enable bit is cleared (these
events ‘reset’ the clock of the GPIO Interrupt flip-flop, which
must be ‘reset’ to ‘0’ before another GPIO interrupt event can
‘clock’ the GPIO Interrupt flip-flop and produce an IRQ).
Note.
If the port pin that triggered an interrupt is held in its
active (trigger) state while its corresponding port interrupt
enable bit is cleared and then set, a GPIO interrupt event
occurs as the GPIO Interrupt flip-flop clock transitions from ‘1’
to ‘0’ and then back to ‘1’ (please refer to
The
USB Controller does not assign interrupt priority to different
port pins and the Port Interrupt Enable Registers are not
cleared during the interrupt acknowledge process. When a
GPIO interrupt is serviced, the ISR must poll the ports to
determine which pin caused the interrupt.
Document #: 38-08026 Rev. *A
Page 12 of 25
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