CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Waveforms
(continued)
First Data Word Latency after Reset with Simultaneous Read and Write
WCLKA,WCLKB
t
DS
DA
0
−
DA
8
(DB
0
−
DB
8
)
t
ENS
WENA1(WENB1)
WENA2(WENB2)
(if applicable)
t
SKEW1
RCLKA(RCLKB)
t
REF
EFA(EFB)
[
16
]
D
0
(FIRSTVALID WRITE)
[
15
]
D
1
D
2
D
3
D
4
t
FRL
t
A
RENA1, RENA2
(RENB1,RENB2)
QA
0
−
QA
8
(QB
0
−
QB
8
)
OEA(OEB)
D
0
t
OLZ
t
OE
t
A
D
1
48X1–9
Notes:
15. When t
SKEW1
> minimum specification, t
FRL
(maximum) = t
CLK
+ t
SKEW1
. When t
SKEW1
< minimum specification, t
FRL
(maximum) = either 2*t
CLK
+ t
SKEW1
or t
CLK
+ t
SKEW1
.
The Latency Timing applies only at the Empty Boundary (EFA, EFB= LOW).
16. The first word is available the cycle after (EFA, EFB) goes HIGH, always.
Document #: 38-06005 Rev. **
Page 9 of 23
CYPRESS [ CYPRESS SEMICONDUCTOR ]
