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CY7C4801-15AC 参数 Datasheet PDF下载

CY7C4801-15AC图片预览
型号: CY7C4801-15AC
PDF下载: 下载PDF文件 查看货源
内容描述: 五百一十二分之二百五十六/ 1K / 2K / 4K / 8K ×9 ×2双同步FIFO的 [256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs]
分类和应用: 先进先出芯片
文件页数/大小: 23 页 / 286 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Characteristics
Over the Operating Range
7C48X1-10
Parameter
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
t
PAE
t
SKEW1
t
SKEW2
Description
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-Up Time
Data Hold Time
Enable Set-Up Time
Enable Hold Time
Reset Pulse Width
[8]
Reset Set-Up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low Z
[9]
Output Enable to Output Valid
Output Enable to Output in High Z
[9]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Full Flag
Skew Time between Read Clock and Write
Clock for Empty Flag and Full Flag
Skew Time between Read Clock and Write
Clock for Almost-Empty Flag and Almost-Full
Flag
5
15
0
3
3
7
7
8
8
8
8
6
15
2
10
4.5
4.5
3.5
0.5
3.5
0.5
10
8
8
10
0
3
3
8
8
10
10
10
10
10
18
Min.
Max.
100
8
2
15
6
6
4
1
4
1
15
10
10
15
0
3
3
12
12
15
15
15
15
12
20
7C48X1-15
Min.
Max.
66.7
10
2
25
10
10
6
1
6
1
25
15
15
25
0
3
3
15
15
20
20
20
20
7C48X1-25
Min.
Max.
40
15
2
35
14
14
7
2
7
2
35
20
20
35
7C48X1-35
Min.
Max.
28.6
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
8. Pulse widths less than minimum values are not allowed.
9. Values guaranteed by design, not currently tested.
Document #: 38-06005 Rev. **
Page 6 of 23