CY7C4425/4205/4215
CY7C4225/4235/4245
Switching Waveforms
(continued)
Read Cycle Timing
t
CLK
t
CLKH
RCLK
t
ENS
REN
t
REF
EF
t
A
Q
0
–Q
17
t
OLZ
t
OE
OE
[14]
t
SKEW2
VALID DATA
t
CLKL
t
ENH
NO OPERATION
t
REF
t
OHZ
WCLK
WEN
42X5–7
Reset Timing
[15]
t
RS
RS
t
RSR
REN, WEN,
LD
t
RSF
EF,PAE
t
RSF
FF,PAF,
HF
t
RSF
Q
0 -
Q
17
OE=0
42X5–8
OE=1
[16]
Notes:
14. .t
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
, then EF may not change state until the next RCLK edge.
15. The clocks (RCLK, WCLK) can be free-running during reset.
16. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
7
CYPRESS [ CYPRESS SEMICONDUCTOR ]
