CY7C4425/4205/4215
CY7C4225/4235/4245
Selection Guide
7C42X5-10
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Operating Current (I
CC2
)
(mA) @ freq=20MHz
Commercial
Industrial
CY7C4205
256 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
100
8
10
3
0.5
8
45
50
CY7C4215
512 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
7C42X5-15
66.7
10
15
4
1
10
45
50
CY7C4225
1K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
7C42X5-25
40
15
25
6
1
15
45
50
CY7C4235
2K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
7C42X5-35
28.6
20
35
7
2
20
45
50
CY7C4245
4K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4425
Density
Packages
64 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
Pin Definitions
Signal Name
D
0–17
Q
0–17
WEN
REN
WCLK
Description
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
I/O
I
O
I
I
I
Data inputs for an 18-bit bus
Data outputs for an 18-bit bus
Enables the WCLK input
Enables the RCLK input
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
Dual-Mode Pin:
Single device or width expansion - Half Full status flag.
Cascaded - Write Expansion Out signal, connected to WXI of next device.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when V
CC
/SMODE is tied
to V
CC
; it is synchronized to RCLK when V
CC
/SMODE is tied to V
SS
.
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V
CC
/SMODE is tied to
V
CC
; it is synchronized to WCLK when V
CC
/SMODE is tied to V
SS
.
When LD is LOW, D
0 - 17
(O
0 - 17
) are written (read) into (from) the programma-
ble-flag-offset register.
Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to V
SS
; all other
devices will have FL tied to V
CC
. In standard mode of width expansion, FL is tied
to V
SS
on all devices.
Not Cascaded - Tied to V
SS
. Retransmit function is also available in standalone
mode by strobing RT.
Cascaded - Connected to WXO of previous device.
Not Cascaded - Tied to V
SS
.
Function
RCLK
Read Clock
I
WXO/HF
Write Expansion
Out/Half Full Flag
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Load
First Load/
Retransmit
O
EF
FF
PAE
O
O
O
PAF
O
LD
FL/RT
I
I
WXI
Write Expansion
Input
I
3
CYPRESS [ CYPRESS SEMICONDUCTOR ]
