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7C342B-15
Parameter
t
AWH
t
AWL
t
ACNT
f
ACNT
Description
Asynchronous Clock Input HIGH Time
[5]
Asynchronous Clock Input LOW Time
[5]
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency
[5]
CY7C342B
7C342B–20
Min.
14
11
20
50
40
25
33.3
Max.
Unit
16
14
Commercial and Industrial External Asynchronous Switching Characteristics
Over Operating Range (continued)
Min.
11
9
Max.
Commercial and Industrial Typical Internal Switching Characteristics
Over Operating Range
7C342B-15
Parameter
t
IN
t
IO
t
EXP
t
LAD
t
LAC
t
OD
t
ZX[8]
t
XZ
t
RSU
t
RH
t
LATCH
t
RD
t
COMB[9]
t
IC
t
ICS
t
FD
t
PRE
t
CLR
t
PIA
t
IN
t
IO
t
EXP
t
LAD
t
LAC
t
OD
t
ZX[8]
t
XZ
t
RSU
t
RH
t
LATCH
t
RD
Description
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
[3]
Output Buffer Enable Delay
[3]
Output Buffer Disable Delay
[7]
Register Set-Up Time Relative to Clock Signal at Register
Register Hold Time Relative to Clock Signal at Register
Flow Through Latch Delay
Register Delay
Transparent Mode Delay
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Programmable Interconnect Array Delay Time
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
[3]
Output Buffer Enable Delay
[3]
Output Buffer Disable Delay
[7]
Register Set-Up Time Relative to Clock Signal at Register
Register Hold Time Relative to Clock Signal at Register
Flow Through Latch Delay
Register Delay
6
4
3
1
2
7
1
1
1
6
0
1
3
3
10
5
6
12
12
10
5
10
10
8
6
4
2
Min.
Max.
3
3
8
8
5
3
5
5
1
10
1
1
1
8
0
1
3
3
13
7
6
14
14
12
5
11
11
10
8
7C342B-20
Min.
Max.
4
4
10
12
5
3
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
7. C1 = 5 pF.
8. Sample tested only for an output change of 500 mV.
9. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial
operation.
Document #: 38-03014 Rev. *B
Page 7 of 14
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