USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
CY7C342B
Commercial and Industrial External Synchronous Switching Characteristics
Over Operating Range
7C342B-15
Parameter
t
PD1
t
PD2
t
SU
t
CO1
t
H
t
WH
t
WL
f
MAX
t
CNT
f
CNT
Description
Dedicated Input to Combinatorial Output Delay
[3]
I/O Input to Combinatorial Output Delay
[3]
Global Clock Set-Up Time
Synchronous Clock Input to Output
Delay
[3]
0
5
5
100
12
83.3
66.7
Input Hold Time from Synchronous Clock Input
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency
[4]
Minimum Global Clock Period
Maximum Internal Global Clock Frequency
[5]
10
8
0
7
7
71.4
15
Min.
Max.
15
25
13
9
7C342B-20
Min.
Max.
20
33
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
ns
MHZ
Commercial and Industrial External Synchronous Switching Characteristics
Over Operating Range
7C342B-25
Parameter
t
PD1
t
PD2
t
SU
t
CO1
t
H
t
WH
t
WL
f
MAX
t
CNT
t
ODH
f
CNT
Description
Dedicated Input to Combinatorial Output
Global Clock Set-Up Time
Synchronous Clock Input to Output Delay
[3]
Input Hold Time from Synchronous Clock Input
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency
[4]
Minimum Global Clock Period
Output Data Hold Time After Clock
Maximum Internal Global Clock
Frequency
[5]
2
50
0
8
8
62.5
20
2
40
Delay
[3]
15
14
0
10
10
50
25
2
33.3
I/O Input to Combinatorial Output Delay
[3]
Min.
Max.
25
40
20
16
0
12.5
12.5
40
30
7C342B-30
Min.
Max.
30
45
25
20
7C342B-35
Min.
Max.
35
55
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
MHz
Commercial and Industrial External Asynchronous Switching Characteristics
Over Operating Range
7C342B-15
Parameter
t
ACO1
t
AS1
t
AH
t
AWH
t
AWL
t
ACNT
f
ACNT
t
ACO1
t
AS1
t
AH
Description
Asynchronous Clock Input to Output Delay
[3]
Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input
[6]
Input Hold Time from Asynchronous Clock Input
Asynchronous Clock Input HIGH
Asynchronous Clock Input LOW
Time
[6]
Time
[6]
5
5
5
5
12
83.3
25
5
6
6
8
66.7
30
10
10
Min.
Max.
15
6
6
7
7
15
7C342B–20
Min.
Max.
20
Unit
ns
ns
ns
ns
ns
ns
MHz
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency
[5]
Asynchronous Clock Input to Output Delay
[3]
Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input
[5]
Input Hold Time from Asynchronous Clock Input
Notes:
3. C1 = 35 pF.
4. The f
MAX
values represent the highest frequency for pipeline data.
5. This parameter is measured with a 16-bit counter programmed into each LAB
6. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the t
AWH
and t
AWL
parameters must be swapped.
Document #: 38-03014 Rev. *B
Page 6 of 14
CYPRESS [ CYPRESS SEMICONDUCTOR ]
