PRELIMINARY
Switching Characteristics
Over the Operating Range
[11, 12, 13]
-166
Parameter
t
CYC
t
CH
t
CL
t
AS
t
AH
t
CO
t
DOH
t
CENS
t
CENH
t
WES
t
WEH
t
ALS
t
ALH
t
DS
t
DH
t
CES
t
CEH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
t
EOV
Description
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-Up Before CLK
Rise
-150
-143
-133
-100
CY7C1352B
-80
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
5.0
1.4
1.4
1.5
6.6
2.5
2.5
1.5
0.5
3.5
1.5
1.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
3.2
1.5
1.5
3.0
0
3.2
0
3.5
3.0
0
4.0
3.2
3.8
1.5
2.0
0.5
2.0
0.5
2.0
0.5
1.7
0.5
2.0
0.5
1.5
1.5
4.0
0
4.2
3.5
7.0
2.8
2.8
2.0
0.5
4.0
1.5
2.0
0.5
2.0
0.5
2.0
0.5
1.7
0.5
2.0
0.5
1.5
1.5
4.2
0
5.0
3.5
7.5
3.0
3.0
2.0
0.5
4.2
1.5
2.2
0.5
2.2
0.5
2.2
0.5
2.0
0.5
2.2
0.5
1.5
1.5
5.0
0
7.0
3.5
10
4.0
4.0
2.2
0.5
5.0
1.5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
1.5
1.5
7.0
5.0
12.5
4.0
4.0
2.5
1.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Hold After CLK Rise 0.5
Data Output Valid After CLK
Rise
Data Output Hold After CLK
Rise
CEN Set-Up Before CLK Rise 1.5
CEN Hold After CLK Rise
GW, BWS
[1:0]
Set-Up Before
CLK Rise
GW, BWS
[1:0]
Hold After CLK
Rise
ADV/LD Set-Up Before CLK
Rise
ADV/LD Hold after CLK Rise
Data Input Set-Up Before
CLK Rise
Data Input Hold After CLK
Rise
Chip Enable Set-Up Before
CLK Rise
Chip Enable Hold After CLK
Rise
Clock to High-Z
[10, 12, 13, 14]
Clock to Low-Z
[10, 12, 13, 14]
OE HIGH to Output High-Z
[10,
12, 13, 14]
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
1.5
OE LOW to Output Low-Z
[10,
12, 13, 14]
OE LOW to Output Valid
[12]
Shaded areas contain advance information.
Notes:
12. t
CHZ
, t
CLZ
, t
OEV
, t
EOLZ
, and t
EOHZ
are specified with A/C test conditions shown in part (a) of AC Test Loads and waveforms. Transition is measured
±
200 mV
from steady-state voltage.
13. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
8
CYPRESS [ CYPRESS SEMICONDUCTOR ]
