PRELIMINARY
Pin Definitions
(continued)
Pin Number
Name
1−3, 6−7, 25,
NC
28−30, 51−53,
56−57, 75, 78−
79, 95−96
83, 84
NC
38, 39, 42, 43
DNU
I/O
-
CY7C1352B
Description
No Connects. These pins are not connected to the internal device.
-
-
No Connects. Reserved for address inputs for depth expansion. Pin 83 is re-
served for 512K depth and pin 84 is reserved for 1-Mb depth devices.
Do Not Use pins. These pins should be left floating or tied to V
SS
.
Burst Read Accesses
The CY7C1352B has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to A
0
−A
17
is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ
[15:0]
and
DP
[1:0]
. In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ
[15:0]
and
DP
[1:0]
(or a subset for byte write operations, see Write Cycle
Description table for details) inputs is latched into the device
and the write is complete.
The data written during the Write operation is controlled by
BWS
[1:0]
signals. The CY7C1352B provides byte write capa-
bility that is described in the write cycle description table. As-
serting the Write Enable input (WE) with the selected Byte
Write Select (BWS
[1:0]
) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-
ple byte write operations.
Because the CY7C1352B is a common I/O device, data should
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before present-
ing data to the DQ
[15:0]
and DP
[1:0]
inputs. Doing so will three-
state the output drivers. As a safety precaution, DQ
[15:0]
and
DP
[1:0]
are automatically three-stated during the data portion
of a write cycle, regardless of the state of OE.
Introduction
Functional Overview
The CY7C1352B is a synchronous-pipelined Burst SRAM de-
signed specifically to eliminate wait states during Write-Read
transitions. All synchronous inputs pass through input regis-
ters controlled by the rising edge of the clock. The clock signal
is qualified with the Clock Enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. All data outputs pass through output registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
CO
) is 3.5 ns (166-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE
1
, CE
2
, CE
3
) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access
can either be a read or write operation, depending on the sta-
tus of the Write Enable (WE). BWS
[1:0]
can be used to conduct
byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been de-
selected in order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs (A
0
−A
17
)
is latched into the Address Register and presented to the
memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the input of the output register. At the
rising edge of the next clock the requested data is allowed to
propagate through the output register and onto the data bus
within 3.5 ns (166-MHz device) provided OE is active LOW.
After the first clock of the read access the output buffers are
controlled by OE and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. During the second clock, a subsequent operation
(Read/Write/Deselect) can be initiated. Deselecting the device
is also pipelined. Therefore, when the SRAM is deselected at
clock rise by one of the chip enable signals, its output will
three-state following the next clock rise.
4
CYPRESS [ CYPRESS SEMICONDUCTOR ]
