CY7C1347F
Interleaved Burst Sequence
First
Address
A
[1:0]
00
01
10
11
Second
Address
A
[1:0]
01
00
11
10
Third
Address
A
[1:0]
10
11
00
01
Fourth
Address
A
[1:0]
11
10
01
00
Linear Burst Sequence
First
Address
A
[1:0]
00
01
10
11
Second
Address
A
[1:0]
01
10
11
00
Third
Address
A
[1:0]
10
11
00
01
Fourth
Address
A
[1:0]
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
Test Conditions
ZZ > V
DD
−
0.2V
ZZ > V
DD
−
0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
0
2t
CYC
2t
CYC
Min.
Max.
40
2t
CYC
Unit
mA
ns
ns
ns
ns
Truth Table
[2, 3, 4, 5, 6]
Next Cycle
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Snooze Mode, Power-down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
Add.
Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
CE
1
H
L
L
L
L
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
CE
2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
CE
3
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP ADSC ADV WRITE
X
L
X
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
OE
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
DQ
CLK
L-H three-state
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
three-state
three-state
three-state
three-state
three-state
Q
three-state
D
Q
three-state
Q
three-state
Q
three-state
D
D
Q
three-state
Q
three-state
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW
A
, BW
B
, BW
C
, BW
D
) and BWE = L or GW = L. WRITE = H when all Byte write enable signals
(BW
A
, BW
B
, BW
C
, BW
D
), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW
[A:D]
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05213 Rev. *D
Page 6 of 19