CY7C132/CY7C136
CY7C142/CY7C146
Switching Characteristics
Over the Operating Range
[6, 11]
(continued)
7C132-35
7C136-35
7C142-35
7C146-35
WRITE CYCLE
[15]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD
t
DDD
t
WDD
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
Data Set-Up to Write End
Data Hold from Write End
R/W LOW to High Z
[10]
R/W HIGH to Low Z
[10]
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
[16]
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
[16]
Port Set Up for Priority
R/W LOW after BUSY LOW
[17]
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
5
0
30
35
Note
18
Note
18
25
25
25
25
25
25
0
20
20
20
20
5
0
35
45
Note
18
Note
18
35
35
35
35
35
35
35
30
30
2
0
25
15
0
20
0
25
25
25
25
5
0
35
45
Note
18
Note
18
45
45
45
45
45
45
45
35
35
2
0
30
20
0
20
0
30
30
30
30
55
40
40
2
0
30
20
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C142-55
7C146-55
BUSY/INTERRUPT TIMING
INTERRUPT TIMING
[19]
t
WINS
t
EINS
t
INS
t
OINR
t
EINR
t
INR
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time
[16]
CE to INTERRUPT Reset Time
[16]
Address to INTERRUPT Reset Time
[16]
ns
ns
ns
ns
ns
ns
Notes:
11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
OL
/I
OH,
and 30-pF load capacitance.
12. AC test conditions use V
OH
= 1.6V and V
OL
= 1.4V.
13. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
14. t
LZCE
, t
LZWE
, t
HZOE
, t
LZOE,
t
HZCE,
and t
HZWE
are tested with C
L
= 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
15. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
17. CY7C142/CY7C146 only.
18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
19. 52-pin PLCC and PQFP versions only.
6
CYPRESS [ CYPRESS SEMICONDUCTOR ]
