CY7C1069AV33
AC Switching Characteristics
Over the Operating Range
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CE
1
LOW/CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[9]
9]
[7]
–10
Description
V
CC
(typical) to the First Access
[8]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW/CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[9]
9]
[9]
9]
–12
Max.
Min.
1
12
10
12
3
10
5
12
6
1
5
6
3
5
6
0
10
12
12
8
8
0
0
8
6
0
3
5
6
Max.
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min.
1
10
3
1
3
0
OE HIGH to High-Z
[
CE
1
LOW/CE
2
HIGH to Low-Z
CE
1
HIGH/CE
2
LOW to High-Z
[
CE
1
LOW/CE
2
HIGH to Power-up
[10]
CE
1
HIGH/CE
2
LOW to Power-down
[10]
10
7
7
0
0
7
5.5
0
3
WE LOW to High-Z
[
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
V
DR
> 2V
3.0V
t
R
Notes:
6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0V). As soon as 1ms (T
power
) after reaching the
minimum operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0V) voltage.
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
8. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t
power
time has to be provided initially before a Read/Write operation is
started.
9. t
HZOE
, t
HZSCE
, t
HZWE
and t
LZOE
, t
LZCE
, and t
LZWE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±200
mV from
steady-state voltage.
10. These parameters are guaranteed by design and are not tested.
11. The internal Write time of the memory is defined by the overlap of
CE
1
LOW/CE
2
HIGH
, and WE LOW. CE
1
and WE must be LOW along with CE
2
HIGH to initiate
a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the Write.
12. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05255 Rev. *F
Page 4 of 9
CYPRESS [ CYPRESS SEMICONDUCTOR ]
