CY7C1069AV33
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[3]
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State
[3]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[3]
................................ –0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.3V
±
0.3V
DC Electrical Characteristics
Over the Operating Range
–10
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW
Voltage
[3]
GND < V
I
< V
CC
V
CC
= Max.,
f = f
MAX
= 1/t
RC
CE
2
< V
IL
,
Max. V
CC
, CE
1
> V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
CE
2
< 0.3V, Max. V
CC
,
CE
1
> V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Input Leakage Current
V
CC
Operating
Supply Current
Automatic CE
Power-down Current
—TTL Inputs
Automatic CE
Power-down Current
—CMOS Inputs
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.0
–0.3
–1
–1
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
275
70
2.0
–0.3
–1
–1
Max.
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
260
70
–12
Max.
Unit
V
V
V
V
µA
µA
mA
mA
Output Leakage Current GND < V
OUT
< V
CC
, Output Disabled
I
SB2
50
50
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
TSOP II
6
8
FBGA
8
10
Unit
pF
pF
AC Test Loads and Waveforms
[5]
50Ω
OUTPUT
Z0 = 50Ω
(a)
V
TH
= 1.5V
30 pF* *Capacitive Load consists of all
components of the test environment
3.3V
OUTPUT
5 pF*
*Including
jig and
scope
(b)
90%
10%
Fall time: > 1V/ns
(c)
Notes:
3. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0V). As soon as 1ms (T
power
) after reaching the
minimum operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0V) voltage.
R1 317
Ω
R2
351Ω
All input pulses
3.3V
GND
Rise time > 1V/ns
90%
10%
Document #: 38-05255 Rev. *F
Page 3 of 9
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