CY7C1031
CY7C1032
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CS is LOW and (2) ADSP is LOW.
ADSP-triggered write cycles are completed in two clock
periods. The address at A
0
through A
15
is loaded into the
address register and address advancement logic and
delivered to the RAM core. The write signal is ignored in this
cycle because the cache tag or other external logic uses this
clock period to perform address comparisons or protection
checks. If the write is allowed to proceed, the write input to the
CY7C1031 and CY7C1032 will be pulled LOW before the next
clock rise. ADSP is ignored if CS is HIGH.
If WH, WL, or both are LOW at the next clock rise, information
presented at DQ
0
–DQ
15
and DP
0
–DP
1
will be written into the
location specified by the address advancement logic. WL
controls the writing of DQ
0
–DQ
7
and DP
0
while WH controls
the writing of DQ
8
–DQ
15
and DP
1
. Because the CY7C1031
and CY7C1032 are common-I/O devices, the output enable
signal (OE) must be deasserted before data from the CPU is
delivered to DQ
0
–DQ
15
and DP
0
–DP
1
. As a safety precaution,
the appropriate data lines are three-stated in the cycle where
WH, WL, or both are sampled LOW, regardless of the state of
the OE input.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at rising edge of the clock: (1) CS is LOW, (2) ADSC
is LOW, and (3) WH or WL are LOW. ADSC-triggered
accesses are completed in a single clock cycle.
The address at A
0
through A
15
is loaded into the address
register and address advancement logic and delivered to the
RAM core. Information presented at DQ
0
–DQ
15
and DP
0
–DP
1
will be written into the location specified by the address
advancement logic. Since the CY7C1031 and the CY7C1032
are common-I/O devices, the output enable signal (OE) must
be deasserted before data from the cache controller is
delivered to the data and parity lines. As a safety precaution,
the appropriate data and parity lines are three-stated in the
cycle where WH and WL are sampled LOW regardless of the
state of the OE input.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CS is LOW, (2) ADSP or ADSC
is LOW, and (3) WH and WL are HIGH. The address at A
0
through A
15
is stored into the address advancement logic and
delivered to the RAM core. If the output enable (OE) signal is
asserted (LOW), data will be available at the data outputs a
maximum of 8.5 ns after clock rise. ADSP is ignored if CS is
HIGH.
Burst Sequences
The CY7C1031 provides a 2-bit wraparound counter, fed by
pins A
0
–A
1
, that implements the Intel 80486 and Pentium
processor’s address burst sequence (see
Table 1).
Note that
the burst sequence depends on the first burst address.
Table 1. Counter Implementation for the Intel Pentium/
80486 Processor’s Sequence
First
Address
A
X + 1
, A
x
00
01
10
11
Second
Address
A
X + 1
, A
x
01
00
11
10
Third
Address
A
X + 1
, A
x
10
11
00
01
Fourth
Address
A
X + 1
, A
x
11
10
01
00
The CY7C1032 provides a 2-bit wraparound counter, fed by
pins A0–A1, that implements a linear address burst sequence
(see
Table 2).
Table 2. Counter Implementation for a Linear Sequence
First
Address
A
X + 1
, A
x
00
01
10
11
Second
Address
A
X + 1
, A
x
01
10
11
00
Third
Address
A
X + 1
, A
x
10
11
00
01
Fourth
Address
A
X + 1
, A
x
11
00
01
10
Document #: 38-05278 Rev. *A
Page 2 of 13
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