CY7C1031
CY7C1032
Switching Waveforms
(continued)
Output Timing (Controlled by WH/ WL)
CLK
t
ADS
ADSC and
ADSP
t
WES
WH, WL
t
WEOZ
DATA OUT
t
WEOV
t
WEH
t
ADSH
t
ADS
t
ADSH
Truth Table
Input
CS
H
H
H
H
H
L
L
L
X
X
X
X
ADSP ADSC
X
L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
H
X
L
L
H
H
H
H
ADV
X
H
L
H
L
X
X
X
L
L
H
H
WH or WL
X
H
H
L
L
X
H
L
L
H
L
H
CLK
L→H N/A
L→H Incremented burst address
L→H Incremented burst address
L→H External
L→H External
L→H External
L→H Incremented burst address
L→H Incremented burst address
Address
Operation
Chip deselected
Read cycle, in burst sequence (ADSP ignored)
Write cycle, in burst sequence (ADSP ignored)
Read cycle, begin burst
Read cycle, begin burst
Write cycle, begin burst
Write cycle, in burst sequence
Read cycle, in burst sequence
L→H Same address as previous cycle Read cycle (ADSP ignored)
L→H Same address as previous cycle Write cycle (ADSP ignored)
L→H Same address as previous cycle Write cycle
L→H Same address as previous cycle Read cycle
Ordering Information
Speed
(ns)
8
10
12
8
10
Ordering Code
CY7C1031-8JC
CY7C1031-10JC
CY7C1031-12JC
CY7C1032-8JC
CY7C1032-10JC
[16]
Package
Name
J69
J69
J69
J69
J69
Package Type
52-lead Plastic Leaded Chip Carrier
52-lead Plastic Leaded Chip Carrier
52-lead Plastic Leaded Chip Carrier
52-lead Plastic Leaded Chip Carrier
52-lead Plastic Leaded Chip Carrier
Operating
Range
Commercial
Commercial
Commercial
Commercial
Commercial
Note:
16. EOL (End of Life).
Document #: 38-05278 Rev. *A
Page 11 of 13
CYPRESS [ CYPRESS SEMICONDUCTOR ]
