CY7C1021
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
255
Ω
R 481
Ω
R 481
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
167
30 pF
R2
255
Ω
GND
< 3 ns
3.0V
90%
10%
90%
10%
< 3 ns
ALL INPUT PULSES
(a)
(b)
1021-3
OUTPUT
Equivalent to: THÉVENIN
EQUIVALENT
1.73V
1021-4
Switching Characteristics
[5]
Over the Operating Range
7C1021-10
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
7C1021-12
Min.
12
Max.
7C1021-15
Min.
15
Max.
7C1021-20
Min.
20
Max.
Unit
ns
20
3
20
9
0
9
3
9
0
20
9
0
9
20
12
12
0
0
12
10
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
12
ns
ns
Description
Min.
10
Max.
10
3
10
5
0
5
3
5
0
10
5
0
5
10
8
7
0
0
7
5
0
3
5
7
8
12
9
8
0
0
8
6
0
3
0
0
3
0
3
12
3
12
6
0
6
3
6
0
12
6
0
6
15
10
10
0
0
10
8
0
3
6
9
15
15
7
7
7
15
7
7
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[6, 7]
Byte Enable to End of Write
WRITE CYCLE
[8]
7
Shaded areas contain preliminary information.
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05054 Rev. **
Page 3 of 9
CYPRESS [ CYPRESS SEMICONDUCTOR ]
