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CY7C028V-25AC 参数 Datasheet PDF下载

CY7C028V-25AC图片预览
型号: CY7C028V-25AC
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 32K / 64K X 16/18双端口静态RAM [3.3V 32K/64K x 16/18 Dual-Port Static RAM]
分类和应用:
文件页数/大小: 18 页 / 456 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Figure 3. AC Test Loads and Waveforms
3.3V
3.3V
R1 = 590Ω
OUTPUT
C = 30 pF
R2 = 435Ω
V
TH
= 1.4V
OUTPUT
C = 30 pF
R
TH
= 250Ω
R1 = 590Ω
OUTPUT
C = 5 pF
R2 = 435Ω
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0V
GND
10%
3 ns
90%
90%
10%
3 ns
(c) Three-State Delay (Load 2)
(Used for t
LZ
, t
HZ
, t
HZWE
, & t
LZWE
including scope and jig)
Switching Characteristics
Over the Operating Range
CY7C027V/027VN/027AV/028V/
CY7C037V/037AV/038V
Parameter
Description
Min
Read Cycle
t
RC
t
AA
t
OHA
t
ACE[7]
t
DOE
t
LZOE[8, 9, 10]
t
HZOE[8, 9, 10]
t
LZCE[8, 9, 10]
t
HZCE[8, 9, 10]
t
PU[10]
t
PD[10]
t
ABE[7]
Write Cycle
t
WC
t
SCE[7]
t
AW
t
HA
t
SA[7]
t
PWE
t
SD
Write Cycle Time
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Setup to Write Start
Write Pulse Width
Data Setup to Write End
15
12
12
0
0
12
10
20
16
16
0
0
17
12
25
20
20
0
0
22
15
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
Byte Enable Access Time
0
15
15
3
10
0
20
20
3
10
3
12
0
25
25
3
15
10
3
12
3
15
15
15
3
20
12
3
15
20
20
3
25
13
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-15
Max
Min
-20
Max
Min
-25
Max
Unit
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
OI
/I
OH
and 30 pF load capacitance.
7. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
SCE
time.
8. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
9. Test conditions used are Load 2.
10. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port,
refer to
Document #: 38-06078 Rev. *B
Page 7 of 18