CY7C024/0241
CY7C025/0251
Switching Waveforms
(continued)
Write Cycle No. 1: R/W Controlled Timing
t
WC
ADDRESS
t
HZOE
OE
t
AW
CE
t
SA
R/W
t
HZWE
DATA OUT
t
PWE
t
HA
t
LZWE
NOTE 34
t
SD
t
HD
NOTE 34
DATA IN
Write Cycle No. 2: CE Controlled Timing
t
WC
ADDRESS
t
AW
CE
t
SA
R/W
t
SCE
t
HA
t
SD
DATA IN
t
HD
Notes:
27. R/W must be HIGH during all address transitions.
28. A write occurs during the overlap (t
SCE
or t
PWE
) of a LOW CE or SEM and a LOW UB or LB.
29. t
HA
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
30. If OE is LOW during a R/W-controlled write cycle, the write pulse width must be the larger of t
PWE
or (t
HZWE
+ t
SD
) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t
SD
. If OE is HIGH during an R/W-controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified t
PWE
.
31. To access RAM, CE = V
IL
, SEM = V
IH
.
32. To access upper byte, CE = V
IL
, UB = V
IL
, SEM = V
IH
.
To access lower byte, CE = V
IL
, LB = V
IL
, SEM = V
IH
.
33. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. During this period, the I/O pins are in the output state, and input signals must not be applied.
35. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06035 Rev. *C
Page 12 of 21
CYPRESS [ CYPRESS SEMICONDUCTOR ]
