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CY7B9911V-5JC 参数 Datasheet PDF下载

CY7B9911V-5JC图片预览
型号: CY7B9911V-5JC
PDF下载: 下载PDF文件 查看货源
内容描述: 高速低电压可编程偏移时钟缓冲器 [High Speed Low Voltage Programmable Skew Clock Buffer]
分类和应用: 时钟
文件页数/大小: 17 页 / 404 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7B9911V
3.3 V RoboClock+™
Switching Characteristics
Over the Operating Range
Parameter
f
NOM
Operating Clock
Frequency in MHz
Description
FS = LOW
FS = MID
FS = HIGH
t
RPWH
t
RPWL
t
U
t
SKEWPR
t
SKEW0
t
SKEW1
t
SKEW2
t
SKEW3
t
SKEW4
t
DEV
t
PD
t
ODCV
t
PWH
t
PWL
t
ORISE
t
OFALL
t
LOCK
t
JR
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched-Pair Skew (XQ0, XQ1)
Zero Output Skew (All Outputs)
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)
Output Skew (Rise-Rise, Fall-Fall, Different Class
Output Skew (Rise-Fall, Nominal-Divided,
Device-to-Device
Skew
–0.5
–1.0
0.0
0.0
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation
Output HIGH Time Deviation from 50%
Output LOW Time Deviation from 50%
Output Rise
Output Fall
PLL Lock
Time
0.15
0.15
RMS
Peak-to-Peak
1.0
1.0
Time
Outputs)
Divided-Inverted)
CY7B9911V-5
Min
15
25
40
5.0
5.0
See
0.1
0.25
0.6
0.5
0.5
0.5
0.25
0.5
0.7
1.0
0.7
1.0
1.25
+0.5
+1.0
2.5
3
1.5
1.5
0.5
25
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
Typ
Max
30
50
110
ns
ns
Unit
MHz
Time
Cycle-to-Cycle Output
Jitter
Notes
11. Test measurement levels for the CY7B9911V are TTL levels (1.5 V to 1.5 V). Test conditions assume signal transition times of 2 ns or less and output loading
as shown in the
unless otherwise specified.
12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay is selected when all are loaded
with 30 pF and terminated with 50Ω to VCC/2 (CY7B9911V).
14. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
15. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
16. CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns.
17. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in
Divide-by-2 or Divide-by-4 mode).
18. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, and so on.)
19. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
20. Specified with outputs loaded with 30 pF. Devices are terminated through 50Ω to VCC/2.tPWH is measured at 2.0 V. tPWL is measured at 0.8 V.
21. tORISE and tOFALL measured between 0.8 V and 2.0 V.
22. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This
parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07408 Rev. *F
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