CY7B9910
CY7B9920
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
C
IN
Input Capacitance
T
A
= 25
°
C, f = 1 MHz, V
CC
= 5.0V
Max
10
Unit
pF
AC Test Loads and Waveforms
5V
R1
C
L
R2
R1=130
R2=91
C
L
= 50 pF (C
L
= 30pF for –5 and – 2 devices)
(Includes fixture and probe capacitance)
7B9910–3
3.0V
2.0V
V
th
=1.5V
0.8V
0.0V
≤1ns
2.0V
V
th
=1.5V
0.8V
≤1ns
7B9910–4
TTL AC Test Load (CY7B9910)
V
CC
R1
C
L
R2
7B9910–5
TTL Input Test Waveform (Cy7B9910)
V
CC
80%
V
th
= V
CC
/2
20%
0.0V
≤
3ns
80%
V
th
= V
CC
/2
20%
≤
3ns
7B9910–6
R1=100
R2=100
C
L
= 50 pF (C
L
=30 pF for –5 and – 2devices)
(Includes fixture and probe capacitance)
CMOS AC Test Load (CY7B9920)
CMOS Input Test Waveform (CY7B9920)
Switching Characteristics
Over the Operating Range
CY7B9910–2
[8]
Parameter
f
NOM
Description
Operating Clock
Frequency in MHz
FS =
FS =
t
RPWH
t
RPWL
t
SKEW
t
DEV
t
PD
t
ODCV
t
ORISE
t
OFALL
t
LOCK
t
JR
REF Pulse Width HIGH
REF Pulse Width LOW
Zero Output Skew (All Outputs)
[13, 14]
Device-to-Device Skew
[14, 15]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation
[16]
Output Rise Time
Output Fall
PLL Lock Time
[17, 18]
CY7B9920–2
[8]
Min
15
25
40
5.0
5.0
Typ
Max
30
50
80
[12]
ns
ns
0.1
–0.25
–0.65
0.5
0.5
0.0
0.0
2.0
2.0
0.25
0.75
+0.25
+0.65
2.5
2.5
0.5
200
25
ns
ns
ns
ns
ns
ns
ms
ps
ps
Unit
MHz
Min
LOW
[1, 2]
Typ
Max
30
50
80
15
25
40
5.0
5.0
0.1
–0.25
–0.65
0.15
0.15
0.0
0.0
1.0
1.0
FS = MID
HIGH
0.25
0.75
+0.25
+0.65
1.2
1.2
0.5
200
25
Time
[17, 18]
[19]
Cycle-to-Cycle Output Jitter Peak to Peak
RMS
Document Number: 38-07135 Rev. *B
Page 5 of 11
CYPRESS [ CYPRESS SEMICONDUCTOR ]
