CY7B923
CY7B933
CY7B923/CY7B933 Electrical Characteristics
Over the Operating Range
[1]
Parameter
V
OHT
V
OLT
I
OST
V
IHT
V
ILT
I
IHT
I
ILT
V
OHE
V
OLE
V
ODIF
Description
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Output HIGH Voltage
(V
CC
referenced)
Output LOW Voltage
(V
CC
referenced)
Output Differential Voltage
|(OUT+)
−
(OUT−)|
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Input Differential Voltage
|(IN+)
−
(IN−)|
Highest Input HIGH Voltage
Lowest Input LOW Voltage
Input HIGH Current
Input LOW Current
Transmitter Power Supply
Current
Receiver Power Supply
Current
V
IN
= V
IHH
Max.
V
IN
= V
ILL
Min.
Freq. = Max.
Freq. = Max.
Com’l
Ind’l & Mil
Com’l
Ind’l & Mil
−200
Typ.
65
75
120
135
Max.
85
95
155
160
mA
mA
mA
mA
2.0
750
V
IN
= V
IHE
Max.
V
IN
= V
ILE
Min.
+0.5
50
V
CC
V
IN
= V
CC
V
IN
= 0.0V
Load = 50Ω to Com’l
V
CC
−
2V
Ind’l & Mil
Load = 50Ω to Com’l
V
CC
−
2V
Ind’l & Mil
Load = 50 ohms to V
CC
−
2V
V
CC
−1.03
V
CC
−1.05
V
CC
−1.86
V
CC
−1.96
0.6
Test Conditions
I
OH
=
−
2 mA
I
OL
= 4 mA
V
OUT
=0V
[2]
Com’l, Ind’l, & Mil
Ind’l & Mil
(CKW and FOTO, only)
−15
2.0
2.2
−0.5
−10
Min.
2.4
0.45
−90
V
CC
V
CC
0.8
+10
−
500
V
CC
−0.83
V
CC
−0.83
V
CC
−1.62
V
CC
−1.62
Max.
Unit
V
V
mA
V
V
V
µA
µA
V
V
V
V
V
TTL OUTs, CY7B923: RP; CY7B933: Q
0−7
, SC/D, RVS, RDY, CKR, SO
TTL INs, CY7B923: D
0−7
, SC/D, SVS, ENA, ENN, CKW, FOTO, BISTEN; CY7B933: RF, REFCLK, BISTEN
Transmitter PECL-Compatible Output Pins: OUTA+, OUTA−, OUTB+, OUTB−, OUTC+, OUTC−
Receiver PECL-Compatible Input Pins: A/B, SI, INB
V
IHE
V
ILE
I
IHE[3]
I
ILE[3]
V
DIFF
V
IHH
V
ILL
I
IHH
I
ILL[4]
I
CCT[5]
I
CCR[6]
Com’l
Ind’l & Mil
Com’l
Ind’l & Mil
V
CC
−1.165
V
CC
−1.14
2.0
2.0
V
CC
V
CC
V
CC
−1.475
V
CC
−1.50
+500
V
V
V
V
µA
µA
mV
V
V
µA
µA
Differential Line Receiver Input Pins: INA+, INA−, INB+, INB−
Miscellaneous
Notes:
1. See the last page of this specification for Group A subgroup testing information.
2. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
3. Applies to A/B only.
4. Input currents are always positive at all voltages above V
CC
/2.
5. Maximum I
CCT
is measured with V
CC
= Max., one PECL output pair loaded with 50 ohms to V
CC
−
2.0V, and other PECL outputs tied to V
CC
. Typical I
CCT
is measured with
V
CC
= 5.0V, T
A
= 25°C, one output pair loaded with 50 ohms to V
CC
−
2.0V, others tied to V
CC
, BISTEN = LOW. I
CCT
includes current into V
CCQ
(pin 9 and pin 22) only. Current
into V
CCN
is determined by PECL load currents, typically 30 mA with 50 ohms to V
CC
−
2.0V. Each additional enabled PECL pair adds 5 mA to I
CCT
and an additional load
current to V
CCN
as described. When calculating the contribution of PECL load currents to chip power dissipation, the output load current should be multiplied by 1V instead of V
CC
.
6. Maximum I
CCR
is measured with V
CC
= Max., RF = LOW, and outputs unloaded. Typical I
CCR
is measured with V
CC
= 5.0V, T
A
= 25°C, RF = LOW, BISTEN = LOW, and
outputs unloaded. I
CCR
includes current into V
CCQ
(pins 21 and 24). Current into V
CCN
(pin 9) is determined by the total TTL output buffer quiescent current plus the sum of all
the load currents for each output pin. The total buffer quiescent current is 10mA max., and max. TTL load current for each output pin can be calculated as follows: Where
I I CCN
+
TTLPin
0.95) (VCCN * 5)*0.3
)
CL
*
RL
VCCN
) 1.5 *
Fpin
* 1.1
2
R
L
=equivalent load resistance, C
L
=capacitive load, and F
pin
=frequency in MHz of data on pin. A derating factor of 1.1 has been included to account for worst
process corner and temperature condition.
8
CYPRESS [ CYPRESS SEMICONDUCTOR ]
