CY7B923
CY7B933
The REFCLK input provides a byte-rate reference frequency
to improve PLL acquisition time and limit unlocked frequency
excursions of the CKR when no data is present at the serial
inputs. The frequency of REFCLK is required to be within
±0.1%
of the frequency of the clock that drives the transmitter
CKW pin.
Framer
Framer logic checks the incoming bit stream for the pattern
that defines the byte boundaries. This combinatorial logic filter
looks for the X3.230 symbol defined as a Special Character
Comma (K28.5). When it is found, the free-running bit counter
in the Clock Synchronization block is synchronously reset to
its initial state, thus framing the data correctly on the correct
byte boundaries.
Random errors that occur in the serial data can corrupt some
data patterns into a bit pattern identical to a K28.5, and thus
cause an erroneous data-framing error. The RF input prevents
this by inhibiting reframing during times when normal message
data is present. When RF is held LOW, the HOTLink receiver
will deserialize the incoming data without trying to reframe the
data to incoming patterns. When RF rises, RDY will be inhibited
until a K28.5 has been detected, after which RDY will resume its
normal function. While RF is HIGH, it is possible that an error could
cause misframing, after which all data will be corrupted. Likewise,
a K28.7 followed by D11.x, D20.x, or an SVS (C0.7) followed by
D11.x will create alias K28.5 characters and cause erroneous fram-
ing. These sequences must be avoided while RF is HIGH.
If RF remains HIGH for greater than 2048 bytes, the framer
converts to double-byte framing, requiring two K28.5 charac-
ters aligned on the same byte boundary within 5 bytes in order
to reframe. Double-byte framing greatly reduces the possibility
of erroneously reframing to an aliased K28.5 character.
Shifter
The Shifter accepts serial inputs from the Serial Data inputs
one bit at a time, as clocked by the Clock Synchronization log-
ic. Data is transferred to the Framer on each bit, and to the
Decode register once per byte.
Decode Register
The Decode register accepts data from the Shifter once per
byte as determined by the logic in the Clock Synchronization
block. It is presented to the Decoder and held until it is trans-
ferred to the output latch.
Decoder
Parallel data is transformed from ANSI-specified X3.230
8B/10B codes back to “raw data” in the Decoder. This block
uses the standard decoder patterns shown in the Valid Data
Characters and Valid Special Character Codes and Sequenc-
es sections of this datasheet. Data patterns are signaled by a
LOW on the SC/D output and Special Character patterns are sig-
naled by a HIGH on the SC/D output. Unused patterns or disparity
errors are signaled as errors by a HIGH on the RVS output and by
specific Special Character codes.
Output Register
The Output register holds the recovered data (Q
0
−
7
, SC/D, and
RVS) and aligns it with the recovered byte clock (CKR). This syn-
chronization insures proper timing to match a FIFO interface or oth-
er logic that requires glitch free and specified output behavior. Out-
puts change synchronously with the rising edge of CKR.
In BIST mode, this register becomes the signature pattern
generator and checker by logically converting itself into a Lin-
ear Feedback Shift Register (LFSR) pattern generator. When
enabled, this LFSR will generate a 511-byte sequence that
includes all Data and Special Character codes, including the
explicit violation symbols. This pattern provides a predictable
but pseudo-random sequence that can be matched to an iden-
tical LFSR in the Transmitter. When synchronized, it checks
each byte in the Decoder with each byte generated by the
LFSR and shows errors at RVS. Patterns generated by the
LFSR are compared after being buffered to the output pins and
then fed back to the comparators, allowing test of the entire
receive function.
In BIST mode, the LFSR is initialized by the first occurrence of
the transmitter BIST loop start code D0.0 (D0.0 is sent only
once per BIST loop). Once the BIST loop has been started,
RVS will be HIGH for pattern mismatches between the re-
ceived sequence and the internally generated sequence.
Code rule violations or running disparity errors that occur as
part of the BIST loop will not cause an error indication. RDY
will pulse HIGH once per BIST loop and can be used to check test
pattern progress. The receiver BIST generator can be reinitialized
by leaving and re-entering BIST mode.
Test Logic
Test logic includes the initialization and control for the Built-In
Self-Test (BIST) generator, the multiplexer for Test mode clock
distribution, and control logic for the decoder. Test logic is dis-
cussed in more detail in the CY7B933 HOTLink Receiver Op-
erating Mode Description
7
CYPRESS [ CYPRESS SEMICONDUCTOR ]
