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CY62256LL-70SNC 参数 Datasheet PDF下载

CY62256LL-70SNC图片预览
型号: CY62256LL-70SNC
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ( 32K ×8 )静态RAM [256K (32K x 8) Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 12 页 / 395 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号CY62256LL-70SNC的Datasheet PDF文件第1页浏览型号CY62256LL-70SNC的Datasheet PDF文件第3页浏览型号CY62256LL-70SNC的Datasheet PDF文件第4页浏览型号CY62256LL-70SNC的Datasheet PDF文件第5页浏览型号CY62256LL-70SNC的Datasheet PDF文件第6页浏览型号CY62256LL-70SNC的Datasheet PDF文件第7页浏览型号CY62256LL-70SNC的Datasheet PDF文件第8页浏览型号CY62256LL-70SNC的Datasheet PDF文件第9页  
CY62256  
Product Portfolio  
Power Dissipation  
Operating, ICC  
Standby, ISB2  
VCC Range (V)  
Typ.[2]  
(mA)  
(µA)  
Speed  
(ns)  
70  
55/70  
70  
55/70  
55  
Product  
Min.  
Max.  
5.5  
Typ.[2]  
28  
Max.  
55  
Typ.[2]  
1
Max.  
5
CY62256  
Commercial  
4.5  
5.0  
CY62256L  
CY62256LL  
CY62256LL  
CY62256LL  
Com’l / Ind’l  
Commercial  
Industrial  
25  
50  
2
50  
5
10  
15  
25  
50  
0.1  
0.1  
0.1  
25  
50  
Automotive  
25  
50  
Pin Configurations  
21  
20  
A
OE  
22  
23  
24  
25  
26  
27  
28  
1
2
3
4
5
0
A
1
CE  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
I/O  
A
2
Narrow SOIC  
Top View  
7
DIP  
I/O  
I/O  
I/O  
I/O  
A
3
6
Top View  
A
4
5
4
3
WE  
TSOP I  
Top View  
A
28  
V
CC  
V
1
A
5
28  
V
CC  
1
5
CC  
GND  
A
5
27 WE  
A
2
27 WE  
A
6
2
I/O  
2
6
A
6
(not to scale)  
A
I/O  
1
26  
A
A7  
3
4
5
6
A
7
A
26  
A
3
4
5
6
7
4
4
I/O  
0
8
A
A
A
25  
3
A
8
25  
3
8
A
A
14  
9
24  
A
24  
A
A
A
A
9
A
13  
6
7
9
2
10  
2
A
A
12  
11  
A
A
23  
22  
A
A
23  
22  
A
10  
1
10  
1
OE  
A
OE  
11  
12  
13  
7
A11  
A10  
11  
7
8
9
A12  
A13  
A14  
I/O0  
I/O1  
I/O2  
7
6
5
4
3
A
0
21  
20  
19  
18  
17  
16 I/O  
15  
A
0
A
21  
20  
19  
18  
17  
16 I/O  
15  
A
8
8
12  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
A9  
A
CE  
I/O  
9
A
CE  
I/O  
9
13  
A8  
TSOP I  
Reverse Pinout  
Top View  
A
10  
11  
12  
13  
14  
A
10  
11  
12  
13  
14  
14  
I/O  
A67  
A
14  
7
7
2
I/O  
I/O  
6
I/O  
6
0
0
GND  
A5  
1
I/O  
I/O  
I/O  
5
I/O  
1
5
1
28  
I/O3  
VCC  
(not to scale)  
I/O  
I/O  
2
27  
26  
25  
24  
23  
I/O4  
I/O5  
I/O6  
I/O7  
CE  
2
4
4
WE  
A4  
I/O  
GND  
I/O  
3
GND  
3
A3  
A2  
A1  
22  
A0  
OE  
Pin Definitions  
Pin Number  
1-10, 21, 23-26  
11-13, 15-19,  
27  
Type  
Input  
Input/Output I/O0-I/O7. Data lines. Used as input or output lines depending on operation  
Description  
A0-A14. Address Inputs  
Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is  
conducted  
20  
22  
Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip  
Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins  
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as  
input data pins  
14  
Ground  
GND. Ground for the device  
28  
Power Supply Vcc. Power supply for the device  
Notes:  
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions  
(T = 25°C, V ). Parameters are guaranteed by design and characterization, and not 100% tested.  
A
CC  
Document #: 38-05248 Rev. *C  
Page 2 of 12  
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